Make: FPGAs

Table of contents

1. Preface
   1. FPGA History
   2. About the Book
   3. Conventions Used in This Book
   4. Using Code Examples
   5. Safari® Books Online
   6. How to Contact Us
   7. Acknowledgments
2. 1. Overview
   1. Papilio
   2. Opal Kelly
   3. Red Pitaya
   4. Numato Lab
   5. Design Flow
      1. Concept Phase
      2. Design Phase
      3. Test Phase
      4. Synthesize Phase
      5. Build Phase
      6. Run Phase
   6. Takeaways
3. 2. Count on It!
   1. Blink LEDs Concept
      1. How It Works
      2. Xilinx ISE WebPACK Installation
   2. Design
      1. Peripheral Breadboard
      2. FPGA Circuit Schematic Design Entry
      3. FPGA Circuit HDL Design Entry
      4. Simulation
      5. Build
         1. Creating the Constraints File
      6. Open Kelly Setup
         1. Setup Test
   3. Clock Frequency Experimentation
   4. Takeaways
4. 3. That’s Refreshing
   1. Stopwatch Concept
      1. How It Works
   2. Design
      1. Peripheral Breadboard
      2. FPGA Circuit
      3. Digital Clock Manager (DCM)
      4. Verilog Code and Concurrency
   3. Simulation
   4. Build
      1. Assigning Physical I/O
   5. Takeaways
5. 4. Testing 1, 2, 3, 4
   1. The Test Bench
      1. Test Bench Anatomy
   2. Reuse
   3. Running the Test Bench Project
      1. Step 1: Selection and Download of Core
      2. Step 2: Documentation
      3. Step 3: RTL
      4. Step 4: Adding Test Bench Files and Running the Simulation
   4. Exploring the Test Bench Project
      1. Overview
   5. Takeaways
6. 5. It Does Not Compute
   1. The CARDIAC Computer Model
   2. Getting Started with VTACH
      1. Numato Elbert V2 Setup
   3. Modifications
      1. Step 1: Device Section
      2. Step 2: Pin Assignments
      3. Step 3: Clocking
      4. Step 4: I/O Polarity
      5. Step 5: Memory Block Update
   4. Design, Build, and Simulation
      1. Simulation
   5. Building and Running
   6. Programing and Assembler
   7. Takeaways
7. 6. It’s a Small World!
   1. System on Chip
   2. SoC Architecture
   3. DesignLab
      1. Installation
   4. Papilio DUO Setup
      1. Step 1: Power Up
      2. Step 2: Select COM Port
      3. Step 3: Create Project
      4. Step 4: Associate Circuit
      5. Step 5: Load FPGA Bit File
      6. Step 6: Compile and Upload Sketch
   5. Getting Started with the DesignLab Video-Audio Player
      1. How It Works
   6. Design
      1. Step 1: Create New DesignLab Project
      2. Step 2: Edit Your Design in Xilinx ISE
      3. Step 3: Add VGA Adapter Block
      4. Step 4: Add Audio Blocks
      5. Step 5: Implement and Generate Bit File
      6. Step 6: Create Sketch, Load, and Run
      7. Experiments
      8. Source Code
   7. Takeaways
8. 7. Just for the Fun of It
   1. Getting Started with VGA-Displayed Arcade Games
      1. How It Works
      2. Loading a Game
      3. Source Code and ROM Files
   2. Getting Started with LED Dot Matrix–Displayed Arcade Games
      1. How It Works
      2. Design
      3. Experiments
      4. Source Code
   3. Takeaways
9. 8. Cha-Ching!
   1. Getting Started with the Bitcoin Miner
      1. How It Works
      2. Design
      3. Source Code
   2. Takeaways
10. 9. I Hear You!
    1. Getting Started with the SDR Receiver
       1. How It Works
       2. Red Pitaya Setup
    2. Loading the SDR
       1. Step 1: Copy Red Pitaya SD Card Image
       2. Step 2: Install SDR Applications on PC
       3. Step 3: Connect Red Pitaya to the Network
       4. Step 4: Run SDR Applications
       5. Source Code
    3. Takeaways
11. A. FPGA Boards
12. B. Papilio AVR Loading
    1. Step 1: Power Up
    2. Step 2: Change Circuit Directive
    3. Step 3: Load FPGA Bit File
    4. Step 4: Change COM Port
    5. Step 5: Compile and Upload Sketch
       1. Serial Monitor
    6. Additional Resources
13. C. Text and Code Editor
14. Index