Memory Systems

J

jitter, 392-93, 402

Joint Electron Device Engineering Council (JEDEC), 465

busses, 318

DRAM technology comparison, 341–42

memory bus organization, 318, 319

on-chip DLL, 342–43

programmable burst length, 342, 344–45

programmable CAS latency, 342, 343–44

SDRAM technology, 332–35

Solid-State Technology Association, 332

jump pointers, 160–61

k

kernel page table (KPT), 920

Kirchoff’s voltage law, 380–81

L

Label Structure, 186, 187

last-level caches (LLC), 246

latency, 7

bandwidth characteristics, 592–93

Column Access Strobe, 429

DDR SDRAM, 22

distribution, transaction ordering effect, 587–90

equalization, 539

FB-DIMM, 536

fixed scheduling, 538–40

Fully-Buffered DIMM (FB-DIMM), 41

idle system, 490

latency-oriented study, 593–96

memory-access ...