book

Memory Systems

by Bruce Jacob, David Wang, Spencer Ng

July 2010

Intermediate to advanced

900 pages

40h 1m

English

Morgan Kaufmann

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Cover
Title page
Table of Contents
In Praise of Memory Systems: Cache, DRAM, Disk
Copyright
Dedication
Inside Front Cover
Preface
OVERVIEW: On Memory Systems and Their Design
Ov.1 Memory SystemsOv.2 Four Anecdotes on Modular DesignOv.3 Cross-Cutting IssuesOv.4 An Example Holistic AnalysisOv.5 What to Expect
Part I: Cache

Chapter 1: An Overview of Cache Principles
1.1 Caches, ‘Caches,’ and “Caches”1.2 Locality Principles1.3 What to Cache, Where to Put It, and How to Maintain It1.4 Insights and Optimizations
Chapter 2: Logical Organization
2.1 Logical Organization: A Taxonomy2.2 Transparently Addressed Caches2.3 Non-Transparently Addressed Caches2.4 Virtual Addressing and Protection2.5 Distributed and Partitioned Caches2.6 Case Studies
Chapter 3: Management of Cache Contents
3.1 Case Studies: On-Line Heuristics3.2 Case Studies: Off-Line Heuristics
3.3 Case Studies: Combined Approaches
3.4 Discussions3.5 Building a Content-Management Solution
Chapter 4: Management of Cache Consistency
4.1 Consistency with Backing Store4.2 Consistency with Self4.3 Consistency with Other Clients
Chapter 5: Implementation Issues
5.1 Overview5.2 SRAM Implementation5.3 Advanced SRAM Topics5.4 Cache Implementation
Chapter 6: Cache Case Studies
6.1 Logical Organization6.2 Pipeline Interface6.3 Case Studies of Detailed Itanium-2 Circuits
Part II: DRAM
Chapter 7: Overview of DRAMs
7.1 DRAM Basics: Internals, Operation7.2 Evolution of the DRAM Architecture7.3 Modern-Day DRAM Standards7.4 Fully Buffered DIMM: A Compromise of Sorts7.5 Issues in DRAM Systems, Briefly
Chapter 8: DRAM Device Organization: Basic Circuits and Architecture
8.1 DRAM Device Organization8.2 DRAM Storage Cells8.3 RAM Array Structures8.4 Differential Sense Amplifier8.5 Decoders and Redundancy8.6 DRAM Device Control Logic8.7 DRAM Device Configuration8.8 Data I/O8.9 DRAM Device Packaging8.10 DRAM Process Technology and Process Scaling Considerations
Chapter 9: DRAM System Signaling and Timing
9.1 Signaling System9.2 Transmission Lines on PCBs9.3 Termination9.4 Signaling9.5 Timing Synchronization9.6 Selected DRAM Signaling and Timing Issues9.7 Summary
Chapter 10: DRAM Memory System Organization
10.1 Conventional Memory System10.2 Basic Nomenclature10.3 Memory Modules10.4 Memory System Topology10.5 Summary
Chapter 11: Basic DRAM Memory-Access Protocol
11.1 Basic DRAM Commands11.2 DRAM Command Interactions11.3 Additional Constraints11.4 Command Timing Summary11.5 Summary
Chapter 12: Evolutionary Developments of DRAM Device Architecture
12.1 DRAM Device Families12.2 Historical-Commodity DRAM Devices12.3 Modern-Commodity DRAM Devices12.4 High Bandwidth Path12.5 Low Latency12.6 Interesting Alternatives
Chapter 13: DRAM Memory Controller
13.1 DRAM Controller Architecture13.2 Row-Buffer-Management Policy13.3 Address Mapping (Translation)13.4 Performance Optimization13.5 Summary
Chapter 14: The Fully Buffered DIMM Memory System
14.1 Introduction14.2 Architecture14.3 Signaling and Timing14.4 Access Protocol14.5 The Advanced Memory Buffer14.6 Reliability, Availability, and Serviceability14.7 FB-DIMM Performance Characteristics14.8 Perspective
Chapter 15: Memory System Design Analysis
15.1 Overview15.2 Workload Characteristics15.3 The RAD Analytical Framework15.4 Simulation-Based Analysis15.5 A Latency-Oriented Study15.6 Concluding Remarks
Part III: Disk
Chapter 16: Overview of Disks
16.1 History of Disk Drives16.2 Principles of Hard Disk Drives16.3 Classifications of Disk Drives16.4 Disk Performance Overview16.5 Future Directions in Disks
Chapter 17: The Physical Layer
17.1 Magnetic Recording17.2 Mechanical and Magnetic Components17.3 Electronics
Chapter 18: The Data Layer
18.1 Disk Blocks and Sectors18.2 Tracks and Cylinders18.3 Address Mapping18.4 Zoned-Bit Recording18.5 Servo18.6 Sector ID and No-ID Formatting18.7 Capacity18.8 Data Rate18.9 Defect Management
Chapter 19: Performance Issues and Design Trade-Offs
19.1 Anatomy of an I/O19.2 Some Basic Principles19.3 BPI vs. TPI19.4 Effect of Drive Capacity19.5 Concentric Tracks vs. Spiral Track19.6 Average Seek
Chapter 20: Drive Interface
20.1 Overview of Interfaces20.2 ATA20.3 Serial ATA20.4 SCSI20.5 Serial SCSI20.6 Fibre Channel20.7 Cost, Performance, and Reliability
Chapter 21: Operational Performance Improvement
21.1 Latency Reduction Techniques21.2 Command Queueing and Scheduling21.3 Reorganizing Data on the Disk21.4 Handling Writes21.5 Data Compression
Chapter 22: The Cache Layer
22.1 Disk Cache22.2 Cache Organizations22.3 Caching Algorithms
Chapter 23: Performance Testing
23.1 Test and Measurement23.2 Basic Tests23.3 Benchmark Tests23.4 Drive Parameters Tests
Chapter 24: Storage Subsystems
24.1 Data Striping24.2 Data Mirroring24.3 RAID24.4 SAN24.5 NAS24.6 iSCSI
Chapter 25: Advanced Topics
25.1 Perpendicular Recording25.2 Patterned Media25.3 Thermally Assisted Recording25.4 Dual Stage Actuator25.5 Adaptive Formatting25.6 Hybrid Disk Drive25.7 Object-Based Storage
Chapter 26: Case Study
26.1 The Mechanical Components26.2 Electronics26.3 Data Layout26.4 Interface26.5 Cache26.6 Performance Testing
Part IV: Cross-Cutting Issues
Chapter 27: The Case for Holistic Design
27.1 Anecdotes, Revisited27.2 Perspective
Chapter 28: Analysis of Cost and Performance
28.1 Combining Cost and Performance28.2 Pareto Optimality28.3 Taking Sampled Averages Correctly28.4 Metrics for Computer Performance28.5 Analytical Modeling and the Miss-Rate Function
Chapter 29: Power and Leakage
29.1 Sources of Leakage in CMOS Devices29.2 A Closer Look at Subthreshold Leakage29.3 νCACTI and Energy/Power Breakdown of Pipelined Nanometer Caches
Chapter 30: Memory Errors and Error Correction
30.1 Types and Causes of Failures30.2 Soft Error Rates and Trends30.3 Error Detection and Correction30.4 Reliability of Non-DRAM Systems30.5 Space Shuttle Memory System
Chapter 31: Virtual Memory
31.1 A Virtual Memory Primer31.2 Implementing Virtual Memory
References
Index

Content preview from Memory Systems

CHAPTER 11

Basic DRAM Memory-Access Protocol

The basic structures of modern DRAM devices and memory system organizations have been described in previous chapters. This chapter continues the examination of the DRAM memory system with a discussion on a basic DRAM memory-access protocol. A DRAM memory-access protocol defines commands and timing constraints that a DRAM memory controller uses to manage the movement of data between itself and DRAM devices. The basic DRAM memory-access protocol described in this chapter is generic in nature, and it can be broadly applied to modern memory systems such as SDRAM, DDR SDRAM, DDR2 SDRAM, and DDR3 SDRAM memory systems. The examination of the generic DRAM memory-access protocol begins by focusing on basic ...

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Memory Systems

by Bruce Jacob, David Wang, Spencer Ng

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