Oversampled ADC Using VCO-Based Quantizers
High-bandwidth and high-resolution analog-to-digital converter (ADC) implementations face many challenges for circuit designers using nanometer-scale CMOS processes, yet the demand for ADC performance is unrelenting. For reconfigurable wireless receivers, continuous-time ∑Δ ADCs offer excellent out-of-band rejection and can simply be configured to trade dynamic range with input bandwidth. However, with limited power supplies and decreasing gain for minimum-size transistors, achieving a large dynamic range for high-speed converters is difficult for classical architectures that rely on precision operational amplifiers and comparators. At the same time, advanced CMOS processes offer very fast switching speed and high transistor density that can be utilized in interesting and unconventional ways.
Voltage-controlled oscillator (VCO)–based quantization carries the very attractive aspect of having a highly digital implementation, and as a result, these structures take full advantage of Moore’s law and the enormous industrial investment in digital process development. Reducing the digital gate delay improves both the resolution of the VCO-based quantizer and the achievable sample rate; a 9-dB improvement in signal-to-quantization noise results from a 50% reduction in gate delay. As such, there has been an increasing ...