Chapter 16
Techniques for the Analysis of Digital Bang-Bang PLLs
16.1 INTRODUCTION
The first investigations into digital frequency synthesis began quite some time ago. In the 1970s, sentences like the following appeared in technical journals: “Owing to the development of large scale integrated digital circuits and to the use of the digital computers in the implementation of communication systems, the digital phase locked loops have emerged from a background of analog loops” [1] and overview papers on the status of the digital phase-locked loops (PLLs) were being published [2,3]. Analytical or semianalytical analyses of PLLs were also published, together with investigations on several loop filter topologies (see, e.g., [4] and [5]).
Despite this research effort, in those years digital PLLs never really took off in practical high-performance applications. The reason could be that because of the lack of a practical low jitter digitally controlled oscillator, the performance achievable with these architectures were far from those of the analog loops. In the 1980s, the development of the charge pump–based PLL, together with the use of type IV phase/frequency detector (see [6]), removed some of the nasty limitations of the analog PLLs loops based on the multiplier phase detector. The advantages of this new analog topology were so evident that it was immediately widely adopted in all state-of-the-art frequency synthesizers. This ...
