The Definitive Guide to ARM® Cortex®-M0 and Cortex-M0+ Processors, 2nd Edition

Index

Note: Page numbers followed by “f” and “t” indicate figures and tables respectively.

A

AAPCS, See ARM Architecture Procedure Call Standard

Access Permission field (AP field), 299, 299t

Accidental switching to ARM^® state, 282

Advanced High-performance Bus Lite (AHB™ Lite), 13, 166

Advanced Microcontroller Bus Architecture (AMBA^®), 23, 32

Advanced Peripheral Bus protocol (APB protocol), 166

AHB™ Lite, See Advanced High-performance Bus Lite

AIRCR, See Application Interrupt and Reset Control Register

Aligned transfers, 180, 180f

ALU status flags, 96, 96t

AMBA^®, See Advanced Microcontroller Bus Architecture

AP field, See Access Permission field

APB protocol, See Advanced Peripheral Bus protocol

API, See Application Programming Interface

Application Interrupt ...