Chapter 10. What’s Next
In this final chapter, we look into the near future and give a preview of some features that are being developed by the Accellera VHDL Technical Committee (the VHDL-TC). The focus of the new features is verification and system-level modeling. From a language perspective, VHDL already provides some support for these modeling tasks, in the form of records, access types (pointers), and protected types (shared variables). The new features being developed include class types, verification data structures, randomization, and functional coverage. As much as possible, the new features will build on existing features in the language. Where no existing features meet a need, the new features added will be designed to integrate with ...
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