June 2019
Intermediate to advanced
752 pages
22h 19m
English
The discussion of power rail I*R voltage drop analysis in Chapter 14, “Power Rail Voltage Drop Analysis,” briefly highlights the need to model both rails associated with the design of power domains, as illustrated in Figure 16.1. The SoC methodology and CAD teams review how to insert the Ron and C elements for the sleepFET cells into the matrices used for static and dynamic I*R analysis.
Figure 16.1 Model for sleep (internal) and global rails for voltage drop analysis.
Leakage currents from state retention ...