Chapter 16. Miscellaneous Electrical Analysis Requirements

16.1 SleepFET Power Rail Analysis

16.1.1 I*R Voltage Drop During Active Power State

The discussion of power rail I*R voltage drop analysis in Chapter 14, “Power Rail Voltage Drop Analysis,” briefly highlights the need to model both rails associated with the design of power domains, as illustrated in Figure 16.1. The SoC methodology and CAD teams review how to insert the Ron and C elements for the sleepFET cells into the matrices used for static and dynamic I*R analysis.

In the figure, three cells are connected between VDD and “GND_int.” Three n-FET are connected between “GND_int” and “GND” rails. The sleep FET cell models are included in the power rail solution matrix for I R drop analysis.

Figure 16.1 Model for sleep (internal) and global rails for voltage drop analysis.

Leakage currents from state retention ...

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