Skip to Main Content
VLSI Design Methodology Development, First Edition
book

VLSI Design Methodology Development, First Edition

by Thomas Dillinger
June 2019
Intermediate to advanced content levelIntermediate to advanced
752 pages
22h 19m
English
Pearson
Content preview from VLSI Design Methodology Development, First Edition

Chapter 16. Miscellaneous Electrical Analysis Requirements

16.1 SleepFET Power Rail Analysis

16.1.1 I*R Voltage Drop During Active Power State

The discussion of power rail I*R voltage drop analysis in Chapter 14, “Power Rail Voltage Drop Analysis,” briefly highlights the need to model both rails associated with the design of power domains, as illustrated in Figure 16.1. The SoC methodology and CAD teams review how to insert the Ron and C elements for the sleepFET cells into the matrices used for static and dynamic I*R analysis.

In the figure, three cells are connected between VDD and “GND_int.” Three n-FET are connected between “GND_int” and “GND” rails. The sleep FET cell models are included in the power rail solution matrix for I R drop analysis.

Figure 16.1 Model for sleep (internal) and global rails for voltage drop analysis.

Leakage currents from state retention ...

Become an O’Reilly member and get unlimited access to this title plus top books and audiobooks from O’Reilly and nearly 200 top publishers, thousands of courses curated by job role, 150+ live events each month,
and much more.
Start your free trial

You might also like

Modern VLSI Design: System-on-Chip Design, Third Edition

Modern VLSI Design: System-on-Chip Design, Third Edition

Wayne Wolf
Digital Logic Design, 4th Edition

Digital Logic Design, 4th Edition

Brian Holdsworth, Clive Woods

Publisher Resources

ISBN: 9780135657645