VLSI Digital Signal Processing Systems: Design and Implementation

16.3    CLOCK SKEW AND CLOCK DISTRIBUTION IN BIT-LEVEL PIPELINED VLSI DESIGNS

The previous section presented various clocking styles that can be used for design of pipelined systems. Bit-level pipelined designs are used in highspeed or low-power applications and the problems of clock skew and clock distribution can be severe due to the large number of registers used. In large systems, the global clock is available to different registers at different times due to the propagation delay of the clock lines. The difference between the time of arrival of the global clock at different registers is referred to as clock skew. In this section, the clock skew problem is formulated and conditions resulting in clock skew are discussed. In addition, techniques are presented for clock distribution that can be used to minimize the clock skew.

16.3.1    Clock Skew

In synchronous systems, clock skew is a problem that grows with the speed and size of the system. As a result, in very high-speed bit-level pipelined systems this becomes a major bottleneck. Therefore, it is necessary to understand thoroughly the effects of clock skew before designing bit-level pipelined systems. In addition, the way the clock skew affects the operation of a system generally depends on the type of clocking style used and on the direction of data transfer with respect to the clock signal.

The issues of clock skew are analyzed with the help of Fig. 16.13 [20]. Here, the computational logic block (CLB) and the register R ...