Antenna and Array Technologies for Future Wireless Ecosystems

5Antenna‐in‐Package Design for Wireless System on a Chip

Y. P. Zhang

School of Electrical and Electronic Engineering, Nanyang Technological University, Singapore, 639798, Singapore

5.1 Introduction

Since the mid‐1990s, complementary metal oxide semiconductor (CMOS) based devices have been the technology driver for the wireless revolution [1]. CMOS processes have enabled full system‐on‐chip (SoC) integration of nomadic wireless devices such as Bluetooth and Wi‐Fi radios. Figure 5.1 shows the die micrographs of a Bluetooth SoC in 0.25‐μm CMOS with the die area of 40 mm² and a Wi‐Fi radio SoC in 0.13‐μm CMOS with the die area of 36 mm² [2, 3]. Note that the sophisticated Wi‐Fi radio comprises two identical dual‐band (2.4 and 5 GHz) transceivers. Hence, it can operate as a 2 × 2 multi‐input multi‐output (MIMO) system to provide increased data rate, robustness, and range.

Full SoC integration is not suitable in all cases. In fact, the radio chip is separate in many cases, especially in cellular mobile networks. Figure 5.2 shows the die micrograph of a phased array transceiver in 28‐nm CMOS with the die area of 2.8 × 2.6 mm² for 5G NR (New Radio) at 28 GHz [4]. Note that the die integrates 8 transmit and receive paths and 86 pads for power, ground, and signals.

The arrival of wireless SoCs or single‐chip radios has called for compatible antenna solutions. Naturally, one would consider the solution of integrating an antenna (or antennas) with other radio circuits on the same die, ...