ARM System Developer's Guide

ARM System Developer's Guide

by Andrew Sloss, Dominic Symes, Chris Wright
Released May 2004
Publisher(s): Morgan Kaufmann
ISBN: 9780080490496

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Book description

Over the last ten years, the ARM architecture has become one of the most pervasive architectures in the world, with more than 2 billion ARM-based processors embedded in products ranging from cell phones to automotive braking systems. A world-wide community of ARM developers in semiconductor and product design companies includes software developers, system designers and hardware engineers. To date no book has directly addressed their need to develop the system and software for an ARM-based system. This text fills that gap.

This book provides a comprehensive description of the operation of the ARM core from a developer’s perspective with a clear emphasis on software. It demonstrates not only how to write efficient ARM software in C and assembly but also how to optimize code. Example code throughout the book can be integrated into commercial products or used as templates to enable quick creation of productive software.

The book covers both the ARM and Thumb instruction sets, covers Intel's XScale Processors, outlines distinctions among the versions of the ARM architecture, demonstrates how to implement DSP algorithms, explains exception and interrupt handling, describes the cache technologies that surround the ARM cores as well as the most efficient memory management techniques. A final chapter looks forward to the future of the ARM architecture considering ARMv6, the latest change to the instruction set, which has been designed to improve the DSP and media processing capabilities of the architecture.

* No other book describes the ARM core from a system and software perspective.
* Author team combines extensive ARM software engineering experience with an in-depth knowledge of ARM developer needs.
* Practical, executable code is fully explained in the book and available on the publisher's Website.
* Includes a simple embedded operating system.

Table of contents

  1. Cover image
  2. Title page
  3. Table of Contents
  4. ABOUT THE AUTHORS
  5. Copyright
  6. PREFACE
  7. Chapter 1: ARM EMBEDDED SYSTEMS
    1. 1.1 THE RISC DESIGN PHILOSOPHY
    2. 1.2 THE ARM DESIGN PHILOSOPHY
    3. 1.3 EMBEDDED SYSTEM HARDWARE
    4. 1.4 EMBEDDED SYSTEM SOFTWARE
    5. 1.5 SUMMARY
  8. Chapter 2: ARM PROCESSOR FUNDAMENTALS
    1. 2.1 REGISTERS
    2. 2.2 CURRENT PROGRAM STATUS REGISTER
    3. 2.3 PIPELINE
    4. 2.4 EXCEPTIONS, INTERRUPTS, AND THE VECTOR TABLE
    5. 2.5 CORE EXTENSIONS
    6. 2.6 ARCHITECTURE REVISIONS
    7. 2.7 ARM PROCESSOR FAMILIES
    8. 2.8 SUMMARY
  9. Chapter 3: INTRODUCTION TO THE ARM INSTRUCTION SET
    1. 3.1 DATA PROCESSING INSTRUCTIONS
    2. 3.2 BRANCH INSTRUCTIONS
    3. 3.3 LOAD-STORE INSTRUCTIONS
    4. 3.4 SOFTWARE INTERRUPT INSTRUCTION
    5. 3.5 PROGRAM STATUS REGISTER INSTRUCTIONS
    6. 3.6 LOADING CONSTANTS
    7. 3.7 ARMV5E EXTENSIONS
    8. 3.8 CONDITIONAL EXECUTION
    9. 3.9 SUMMARY
  10. Chapter 4: INTRODUCTION TO THE THUMB INSTRUCTION SET
    1. 4.1 THUMB REGISTER USAGE
    2. 4.2 ARM-THUMB INTERWORKING
    3. 4.3 OTHER BRANCH INSTRUCTIONS
    4. 4.4 DATA PROCESSING INSTRUCTIONS
    5. 4.5 SINGLE-REGISTER LOAD-STORE INSTRUCTIONS
    6. 4.6 MULTIPLE-REGISTER LOAD-STORE INSTRUCTIONS
    7. 4.7 STACK INSTRUCTIONS
    8. 4.8 SOFTWARE INTERRUPT INSTRUCTION
    9. 4.9 SUMMARY
  11. Chapter 5: EFFICIENT C PROGRAMMING
    1. 5.1 OVERVIEW OF C COMPILERS AND OPTIMIZATION
    2. 5.2 BASIC C DATA TYPES
    3. 5.3 C LOOPING STRUCTURES
    4. 5.4 REGISTER ALLOCATION
    5. 5.5 FUNCTION CALLS
    6. 5.6 POINTER ALIASING
    7. 5.7 STRUCTURE ARRANGEMENT
    8. 5.8 BIT-FIELDS
    9. 5.9 UNALIGNED DATA AND ENDIANNESS
    10. 5.10 DIVISION
    11. 5.11 FLOATING POINT
    12. 5.12 INLINE FUNCTIONS AND INLINE ASSEMBLY
    13. 5.13 PORTABILITY ISSUES
    14. 5.14 SUMMARY
  12. Chapter 6: WRITING AND OPTIMIZING ARM ASSEMBLY CODE
    1. 6.1 WRITING ASSEMBLY CODE
    2. 6.2 PROFILING AND CYCLE COUNTING
    3. 6.3 INSTRUCTION SCHEDULING
    4. 6.4 REGISTER ALLOCATION
    5. 6.5 CONDITIONAL EXECUTION
    6. 6.6 LOOPING CONSTRUCTS
    7. 6.7 BIT MANIPULATION
    8. 6.8 EFFICIENT SWITCHES
    9. 6.9 HANDLING UNALIGNED DATA
    10. 6.10 SUMMARY
  13. Chapter 7: OPTIMIZED PRIMITIVES
    1. 7.1 DOUBLE-PRECISION INTEGER MULTIPLICATION
    2. 7.2 INTEGER NORMALIZATION AND COUNT LEADING ZEROS
    3. 7.3 DIVISION
    4. 7.4 SQUARE ROOTS
    5. 7.5 TRANSCENDENTAL FUNCTIONS: LOG, EXP, SIN, COS
    6. 7.6 ENDIAN REVERSAL AND BIT OPERATIONS
    7. 7.7 SATURATED AND ROUNDED ARITHMETIC
    8. 7.8 RANDOM NUMBER GENERATION
    9. 7.9 SUMMARY
  14. Chapter 8: DIGITAL SIGNAL PROCESSING
    1. 8.1 REPRESENTING A DIGITAL SIGNAL
    2. 8.2 INTRODUCTION TO DSP ON THE ARM
    3. 8.3 FIR FILTERS
    4. 8.4 IIR FILTERS
    5. 8.5 THE DISCRETE FOURIER TRANSFORM
    6. 8.6 SUMMARY
  15. Chapter 9: EXCEPTION AND INTERRUPT HANDLING
    1. 9.1 EXCEPTION HANDLING
    2. 9.2 INTERRUPTS
    3. 9.3 INTERRUPT HANDLING SCHEMES
    4. 9.4 SUMMARY
  16. Chapter 10: FIRMWARE
    1. 10.1 FIRMWARE AND BOOTLOADER
    2. 10.2 EXAMPLE: SANDSTONE
    3. 10.3 SUMMARY
  17. Chapter 11: EMBEDDED OPERATING SYSTEMS
    1. 11.1 FUNDAMENTAL COMPONENTS
    2. 11.2 EXAMPLE: SIMPLE LITTLE OPERATING SYSTEM
    3. 11.3 SUMMARY
  18. Chapter 12: CACHES
    1. 12.1 THE MEMORY HIERARCHY AND CACHE MEMORY
    2. 12.2 CACHE ARCHITECTURE
    3. 12.3 CACHE POLICY
    4. 12.4 COPROCESSOR 15 AND CACHES
    5. 12.5 FLUSHING AND CLEANING CACHE MEMORY
    6. 12.6 CACHE LOCKDOWN
    7. 12.7 CACHES AND SOFTWARE PERFORMANCE
    8. 12.8 SUMMARY
  19. Chapter 13: MEMORY PROTECTION UNITS
    1. 13.1 PROTECTED REGIONS
    2. 13.2 INITIALIZING THE MPU, CACHES, AND WRITE BUFFER
    3. 13.3 DEMONSTRATION OF AN MPU SYSTEM
    4. 13.4 SUMMARY
  20. Chapter 14: MEMORY MANAGEMENT UNITS
    1. 14.1 MOVING FROM AN MPU TO AN MMU
    2. 14.2 HOW VIRTUAL MEMORY WORKS
    3. 14.3 DETAILS OF THE ARM MMU
    4. 14.4 PAGE TABLES
    5. 14.5 THE TRANSLATION LOOKASIDE BUFFER
    6. 14.6 DOMAINS AND MEMORY ACCESS PERMISSION
    7. 14.7 THE CACHES AND WRITE BUFFER
    8. 14.8 COPROCESSOR 15 AND MMU CONFIGURATION
    9. 14.9 THE FAST CONTEXT SWITCH EXTENSION
    10. 14.10 DEMONSTRATION: A SMALL VIRTUAL MEMORY SYSTEM
    11. 14.11 THE DEMONSTRATION AS MMUSLOS
    12. 14.12 SUMMARY
  21. Chapter 15: THE FUTURE OF THE ARCHITECTURE
    1. 15.1 ADVANCED DSP AND SIMD SUPPORT IN ARMv6
    2. 15.2 SYSTEM AND MULTIPROCESSOR SUPPORT ADDITIONS TO ARMv6
    3. 15.3 ARMv6 IMPLEMENTATIONS
    4. 15.4 FUTURE TECHNOLOGIES BEYOND ARMv6
    5. 15.5 SUMMARY
  22. Appendix A: ARM AND THUMB ASSEMBLER INSTRUCTIONS
  23. Appendix B: ARM AND THUMB INSTRUCTION ENCODINGS
  24. Appendix C: PROCESSORS AND ARCHITECTURE
  25. Appendix D: INSTRUCTION CYCLE TIMINGS
  26. Appendix E: SUGGESTED READING
  27. INDEX

Product information

  • Title: ARM System Developer's Guide
  • Author(s): Andrew Sloss, Dominic Symes, Chris Wright
  • Release date: May 2004
  • Publisher(s): Morgan Kaufmann
  • ISBN: 9780080490496