book

ARM System Developer's Guide

by Andrew Sloss, Dominic Symes, Chris Wright

May 2004

Intermediate to advanced

689 pages

16h 14m

English

Morgan Kaufmann

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Cover image
Title page
Table of Contents
ABOUT THE AUTHORS
Copyright
PREFACE
Chapter 1: ARM EMBEDDED SYSTEMS
1.1 THE RISC DESIGN PHILOSOPHY1.2 THE ARM DESIGN PHILOSOPHY1.3 EMBEDDED SYSTEM HARDWARE1.4 EMBEDDED SYSTEM SOFTWARE1.5 SUMMARY
Chapter 2: ARM PROCESSOR FUNDAMENTALS
2.1 REGISTERS2.2 CURRENT PROGRAM STATUS REGISTER2.3 PIPELINE2.4 EXCEPTIONS, INTERRUPTS, AND THE VECTOR TABLE2.5 CORE EXTENSIONS2.6 ARCHITECTURE REVISIONS2.7 ARM PROCESSOR FAMILIES2.8 SUMMARY
Chapter 3: INTRODUCTION TO THE ARM INSTRUCTION SET
3.1 DATA PROCESSING INSTRUCTIONS3.2 BRANCH INSTRUCTIONS3.3 LOAD-STORE INSTRUCTIONS3.4 SOFTWARE INTERRUPT INSTRUCTION3.5 PROGRAM STATUS REGISTER INSTRUCTIONS3.6 LOADING CONSTANTS3.7 ARMV5E EXTENSIONS3.8 CONDITIONAL EXECUTION3.9 SUMMARY
Chapter 4: INTRODUCTION TO THE THUMB INSTRUCTION SET
4.1 THUMB REGISTER USAGE4.2 ARM-THUMB INTERWORKING4.3 OTHER BRANCH INSTRUCTIONS4.4 DATA PROCESSING INSTRUCTIONS4.5 SINGLE-REGISTER LOAD-STORE INSTRUCTIONS4.6 MULTIPLE-REGISTER LOAD-STORE INSTRUCTIONS4.7 STACK INSTRUCTIONS4.8 SOFTWARE INTERRUPT INSTRUCTION4.9 SUMMARY

Chapter 5: EFFICIENT C PROGRAMMING
5.1 OVERVIEW OF C COMPILERS AND OPTIMIZATION5.2 BASIC C DATA TYPES5.3 C LOOPING STRUCTURES5.4 REGISTER ALLOCATION5.5 FUNCTION CALLS5.6 POINTER ALIASING5.7 STRUCTURE ARRANGEMENT5.8 BIT-FIELDS5.9 UNALIGNED DATA AND ENDIANNESS5.10 DIVISION5.11 FLOATING POINT5.12 INLINE FUNCTIONS AND INLINE ASSEMBLY5.13 PORTABILITY ISSUES5.14 SUMMARY
Chapter 6: WRITING AND OPTIMIZING ARM ASSEMBLY CODE
6.1 WRITING ASSEMBLY CODE6.2 PROFILING AND CYCLE COUNTING6.3 INSTRUCTION SCHEDULING6.4 REGISTER ALLOCATION6.5 CONDITIONAL EXECUTION6.6 LOOPING CONSTRUCTS6.7 BIT MANIPULATION6.8 EFFICIENT SWITCHES6.9 HANDLING UNALIGNED DATA6.10 SUMMARY
Chapter 7: OPTIMIZED PRIMITIVES
7.1 DOUBLE-PRECISION INTEGER MULTIPLICATION7.2 INTEGER NORMALIZATION AND COUNT LEADING ZEROS7.3 DIVISION7.4 SQUARE ROOTS7.5 TRANSCENDENTAL FUNCTIONS: LOG, EXP, SIN, COS7.6 ENDIAN REVERSAL AND BIT OPERATIONS7.7 SATURATED AND ROUNDED ARITHMETIC7.8 RANDOM NUMBER GENERATION7.9 SUMMARY
Chapter 8: DIGITAL SIGNAL PROCESSING
8.1 REPRESENTING A DIGITAL SIGNAL8.2 INTRODUCTION TO DSP ON THE ARM8.3 FIR FILTERS8.4 IIR FILTERS8.5 THE DISCRETE FOURIER TRANSFORM8.6 SUMMARY
Chapter 9: EXCEPTION AND INTERRUPT HANDLING
9.1 EXCEPTION HANDLING9.2 INTERRUPTS9.3 INTERRUPT HANDLING SCHEMES9.4 SUMMARY
Chapter 10: FIRMWARE
10.1 FIRMWARE AND BOOTLOADER10.2 EXAMPLE: SANDSTONE10.3 SUMMARY
Chapter 11: EMBEDDED OPERATING SYSTEMS
11.1 FUNDAMENTAL COMPONENTS11.2 EXAMPLE: SIMPLE LITTLE OPERATING SYSTEM11.3 SUMMARY
Chapter 12: CACHES
12.1 THE MEMORY HIERARCHY AND CACHE MEMORY12.2 CACHE ARCHITECTURE12.3 CACHE POLICY12.4 COPROCESSOR 15 AND CACHES12.5 FLUSHING AND CLEANING CACHE MEMORY12.6 CACHE LOCKDOWN12.7 CACHES AND SOFTWARE PERFORMANCE12.8 SUMMARY
Chapter 13: MEMORY PROTECTION UNITS
13.1 PROTECTED REGIONS13.2 INITIALIZING THE MPU, CACHES, AND WRITE BUFFER13.3 DEMONSTRATION OF AN MPU SYSTEM13.4 SUMMARY
Chapter 14: MEMORY MANAGEMENT UNITS
14.1 MOVING FROM AN MPU TO AN MMU14.2 HOW VIRTUAL MEMORY WORKS14.3 DETAILS OF THE ARM MMU14.4 PAGE TABLES14.5 THE TRANSLATION LOOKASIDE BUFFER14.6 DOMAINS AND MEMORY ACCESS PERMISSION14.7 THE CACHES AND WRITE BUFFER14.8 COPROCESSOR 15 AND MMU CONFIGURATION14.9 THE FAST CONTEXT SWITCH EXTENSION14.10 DEMONSTRATION: A SMALL VIRTUAL MEMORY SYSTEM14.11 THE DEMONSTRATION AS MMUSLOS14.12 SUMMARY
Chapter 15: THE FUTURE OF THE ARCHITECTURE
15.1 ADVANCED DSP AND SIMD SUPPORT IN ARMv615.2 SYSTEM AND MULTIPROCESSOR SUPPORT ADDITIONS TO ARMv615.3 ARMv6 IMPLEMENTATIONS15.4 FUTURE TECHNOLOGIES BEYOND ARMv615.5 SUMMARY
Appendix A: ARM AND THUMB ASSEMBLER INSTRUCTIONS
Appendix B: ARM AND THUMB INSTRUCTION ENCODINGS
Appendix C: PROCESSORS AND ARCHITECTURE
Appendix D: INSTRUCTION CYCLE TIMINGS
Appendix E: SUGGESTED READING
INDEX

Content preview from ARM System Developer's Guide

CHAPTER 13

MEMORY PROTECTION UNITS

13.1. PROTECTED REGIONS

13.1.1. Overlapping Regions

13.1.2. Background Regions

13.2. INITIALIZING THE MPU, CACHES, AND WRITE BUFFER

13.2.1. Defining Region Size and Location

13.2.2. Access Permission

13.2.3. Setting Region Cache and Write Buffer Attributes

13.2.4. Enabling Regions and the MPU

13.3. DEMONSTRATION OF AN MPU SYSTEM

13.3.1. System Requirements

13.3.2. Assigning Regions Using a Memory Map

13.3.3. Initializing the MPU

13.3.4. Initializing and Configuring a Region

13.3.5. Putting It All Together, Initializing the MPU

13.3.6. A Protected Context Switch

13.3.7. mpuSLOS

13.4. SUMMARY

Some embedded systems use a multitasking operating or control system and must ensure that a running task ...

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ARM System Developer's Guide

by Andrew Sloss, Dominic Symes, Chris Wright

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