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Computer Organization and Design MIPS Edition, 6th Edition

by David A. Patterson, John L. Hennessy

November 2020

Intermediate to advanced

832 pages

37h 45m

English

Morgan Kaufmann

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About This BookAbout the Other BookChanges for the Sixth EditionInstructor SupportConcluding RemarksAcknowledgments for the Sixth Edition
1.1 Introduction1.2 Seven Great Ideas in Computer Architecture1.3 Below Your Program1.4 Under the Covers1.5 Technologies for Building Processors and Memory1.6 Performance1.7 The Power Wall1.8 The Sea Change: The Switch from Uniprocessors to Multiprocessors1.9 Real Stuff: Benchmarking the Intel Core i71.10 Going Faster: Matrix Multiply in Python1.11 Fallacies and Pitfalls1.12 Concluding Remarks Historical Perspective and Further Reading1.13 Historical Perspective and Further Reading1.14 Self-Study1.15 Exercises
2.1 Introduction2.2 Operations of the Computer Hardware2.3 Operands of the Computer Hardware2.4 Signed and Unsigned Numbers2.5 Representing Instructions in the Computer2.6 Logical Operations2.7 Instructions for Making Decisions2.8 Supporting Procedures in Computer Hardware2.9 Communicating with People
2.11 Parallelism and Instructions: Synchronization2.12 Translating and Starting a Program2.13 A C Sort Example to Put It All Together2.14 Arrays versus Pointers

2.15 Advanced Material: Compiling C and Interpreting Java2.16 Real Stuff: ARMv7 (32-bit) Instructions2.17 Real Stuff: ARMv8 (64-bit) Instructions2.18 Real Stuff: RISC-V Instructions2.19 Real Stuff: x86 Instructions2.20 Going Faster: Matrix Multiply in C2.21 Fallacies and Pitfalls2.22 Concluding Remarks Historical Perspective and Further Reading2.21 Historical Perspective and Further Reading2.24 Self-Study2.25 Exercises
3.1 Introduction3.2 Addition and Subtraction3.3 Multiplication3.4 Division3.5 Floating Point3.6 Parallelism and Computer Arithmetic: Subword Parallelism3.7 Real Stuff: Streaming SIMD Extensions and Advanced Vector Extensions in x863.8 Going Faster: Subword Parallelism and Matrix Multiply3.9 Fallacies and Pitfalls3.10 Concluding Remarks Historical Perspective and Further Reading3.11 Historical Perspective and Further Reading3.12 Self-Study3.13 Exercises
4.1 Introduction4.2 Logic Design Conventions4.3 Building a Datapath4.4 A Simple Implementation Scheme A Multicycle Implementation4.5 A Multicycle Implementation4.6 An Overview of Pipelining4.7 Pipelined Datapath and Control4.8 Data Hazards: Forwarding versus Stalling
4.10 Exceptions4.11 Parallelism via Instructions4.12 Putting It All Together: The Intel Core i7 6700 and ARM Cortex-A53The ARM Cortex-A53Performance of the A53 PipelineThe Intel Core i7 6700Performance of the i74.13 Going Faster: Instruction-Level Parallelism and Matrix Multiply Advanced Topic: an Introduction to Digital Design Using a Hardware Design Language to Describe and Model a Pipeline and More Pipelining Illustrations4.14 An Introduction to Digital Design Using a Hardware Design Language to Describe and Model a Pipeline and More Pipelining Illustrations4.15 Fallacies and Pitfalls4.16 Concluding Remarks Historical Perspective and Further Reading4.17 Historical Perspective and Further Reading4.18 Self StudySelf-Study Answers4.19 Exercises
5.1 Introduction5.2 Memory Technologies5.3 The Basics of Caches5.4 Measuring and Improving Cache Performance5.5 Dependable Memory Hierarchy5.6 Virtual Machines5.7 Virtual Memory
5.9 Using a Finite-State Machine to Control a Simple Cache5.10 Parallelism and Memory Hierarchy: Cache Coherence Parallelism and Memory Hierarchy: Redundant Arrays of Inexpensive Disks5.11 Parallelism and the Memory Hierarchy: Redundant Arrays of Inexpensive Disks Advanced Material: Implementing Cache Controllers5.12 Advanced Material: Implementing Cache Controllers
Performance of the Cortex-A53 and Core i7 Memory Hierarchies5.14 Going Faster: Cache Blocking and Matrix Multiply5.15 Fallacies and Pitfalls5.16 Concluding Remarks Historical Perspective and Further Reading5.17 Historical Perspective and Further Reading5.18 Self-StudySelf-Study Answers5.19 Exercises
6.1 Introduction6.2 The Difficulty of Creating Parallel Processing Programs6.3 SISD, MIMD, SIMD, SPMD, and Vector6.4 Hardware Multithreading6.5 Multicore and Other Shared Memory Multiprocessors6.6 Introduction to Graphics Processing Units6.7 Domain Specific Architectures6.8 Clusters, Warehouse Scale Computers, and Other Message-Passing Multiprocessors
Communicating to the Outside World: Cluster Networking6.10 Communicating to the Outside World: Cluster Networking6.11 Multiprocessor Benchmarks and Performance Models6.12 Real Stuff: Benchmarking the Google TPUv3 Supercomputer and an NVIDIA Volta GPU Cluster6.13 Going Faster: Multiple Processors and Matrix Multiply6.14 Fallacies and Pitfalls6.15 Concluding Remarks Historical Perspective and Further Reading6.16 Historical Perspective and Further Reading6.17 Self-StudyAnswers to Self-Study6.18 Exercises
A.1 IntroductionA.2 AssemblersA.3 LinkersA.4 LoadingA.5 Memory UsageA.6 Procedure Call ConventionA.7 Exceptions and InterruptsA.8 Input and OutputA.9 SPIMA.10 MIPS R2000 Assembly LanguageA.11 Concluding RemarksA.12 ExercisesFurther Reading
B.1 IntroductionB.2 Gates, Truth Tables, and Logic EquationsB.3 Combinational LogicB.4 Using a Hardware Description LanguageB.5 Constructing a Basic Arithmetic Logic UnitB.6 Faster Addition: Carry Lookahead
B.8 Memory Elements: Flip-Flops, Latches, and RegistersB.9 Memory Elements: SRAMs and DRAMsB.10 Finite-State MachinesB.11 Timing MethodologiesB.12 Field Programmable DevicesB.13 Concluding RemarksB.14 ExercisesFurther Reading
C.1 IntroductionC.2 GPU System ArchitecturesC.3 Programming GPUsC.4 Multithreaded Multiprocessor ArchitectureC.5 Parallel Memory SystemC.6 Floating-point ArithmeticC.7 Real Stuff: The NVIDIA GeForce 8800C.8 Real Stuff: Mapping Applications to GPUsC.9 Fallacies and PitfallsC.10 Concluding RemarksC.11 Historical Perspective and Further ReadingFurther Reading
D.1 IntroductionD.2 Implementing Combinational Control UnitsD.3 Implementing Finite-State Machine ControlD.4 Implementing the Next-State Function with a SequencerD.5 Translating a Microprogram to HardwareD.6 Concluding RemarksD.7 Exercises
E.1 IntroductionE.2 A Survey of RISC Architectures for Desktop, Server, and Embedded ComputersE.3 The Intel 80x86E.4 The VAX ArchitectureE.5 The IBM 360/370 Architecture for Mainframe ComputersE.6 Historical Perspective and References

Overview

Computer Organization and Design: The Hardware/Software Interface, Sixth Edition, the leading, award-winning textbook from Patterson and Hennessy used by more than 40,000 students per year, continues to present the most comprehensive and readable introduction to this core computer science topic. Improvements to this new release include new sections in each chapter on Domain Specific Architectures (DSA) and updates on all real-world examples that keep it fresh and relevant for a new generation of students.

Covers parallelism in-depth, with examples and content highlighting parallel hardware and software topics
Includes new sections in each chapter on Domain Specific Architectures (DSA)
Discusses and highlights the "Eight Great Ideas" of computer architecture, including Performance via Parallelism, Performance via Pipelining, Performance via Prediction, Design for Moore's Law, Hierarchy of Memories, Abstraction to Simplify Design, Make the Common Case Fast and Dependability via Redundancy