Digital Design and Computer Architecture, ARM Edition

Figure 4.17 Synchronizer circuit

HDL Example 4.20

Synchronizer

SystemVerilog

module sync(input  logic  clk,

       input  logic  d,

       output logic q);

 logic n1;

 always_ff @(posedge clk)

   begin

   n1 <= d; // nonblocking

   q <= n1; // nonblocking

   end

endmodule

Notice that the begin/end construct is necessary because multiple statements appear in the always statement. This is analogous to {} in C or Java. The begin/end was not needed in the flopr example because if/else counts as a single statement.

VHDL

library IEEE; use IEEE.STD_LOGIC_1164.all;

entity sync is

 port(clk: in STD_LOGIC;

    d:  in STD_LOGIC;

    q:  out STD_LOGIC);

end;

architecture ...