book

Digital Design and Computer Architecture, ARM Edition

by Sarah Harris, David Harris

April 2015

Intermediate to advanced

584 pages

21h 24m

English

Morgan Kaufmann

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FeaturesOnline SupplementsHow to Use the Software Tools in a CourseLabsBugsAcknowledgments
1.1 The Game Plan1.2 The Art of Managing Complexity1.3 The Digital Abstraction1.4 Number Systems1.5 Logic Gates1.6 Beneath the Digital Abstraction1.7 CMOS Transistors*1.8 Power Consumption*1.9 Summary and a Look AheadExercisesInterview Questions
2.1 Introduction2.2 Boolean Equations2.3 Boolean Algebra2.4 From Logic to Gates2.5 Multilevel Combinational Logic2.6 X's and Z's, Oh My2.7 Karnaugh Maps2.8 Combinational Building Blocks2.9 Timing2.10 SummaryExercisesInterview Questions
3.1 Introduction3.2 Latches and Flip-Flops3.3 Synchronous Logic Design3.4 Finite State Machines3.5 Timing of Sequential Logic3.6 Parallelism3.7 SummaryExercisesInterview Questions

4.1 Introduction4.2 Combinational Logic4.3 Structural Modeling4.4 Sequential Logic
4.6 Finite State Machines4.7 Data Types*4.8 Parameterized Modules*4.9 Testbenches4.10 SummaryExercisesSystemVerilog ExercisesVHDL ExercisesInterview Questions
5.1 Introduction5.2 Arithmetic Circuits5.3 Number Systems5.4 Sequential Building Blocks5.5 Memory Arrays5.6 Logic Arrays5.7 SummaryExercisesInterview Questions
6.1 Introduction6.2 Assembly Language6.3 Programming6.4 Machine Language
6.6 Odds and Ends*6.7 Evolution of ARM Architecture6.8 Another Perspective: x86 Architecture6.9 SummaryExercisesInterview Questions
7.1 Introduction7.2 Performance Analysis7.3 Single-Cycle Processor7.4 Multicycle Processor
7.6 HDL Representation*7.7 Advanced Microarchitecture*7.8 Real-World Perspective: Evolution of ARM Microarchitecture*7.9 SummaryExercisesInterview Questions
8.1 Introduction8.2 Memory System Performance Analysis8.3 Caches8.4 Virtual Memory8.5 SummaryEpilogueExercisesInterview Questions
9.1 Introduction
9.1 Introduction9.2 Memory-Mapped I/O9.3 Embedded I/O Systems9.4 Other Microcontroller Peripherals9.5 Bus Interfaces9.6 PC I/O Systems9.7 Summary
A.1 Introduction
A.1 IntroductionA.2 74xx LogicA.3 Programmable LogicA.4 Application-Specific Integrated CircuitsA.5 Data SheetsA.6 Logic FamiliesA.7 Packaging and AssemblyA.8 Transmission LinesA.9 Economics
B.1 Data-processing InstructionsB.2 Memory InstructionsB.3 Branch InstructionsB.4 Miscellaneous InstructionsB.5 Condition Flags
C.1 Introduction
C.1 IntroductionSummaryC.2 Welcome to CSummaryC.3 CompilationSummaryC.4 VariablesSummaryC.5 OperatorsC.6 Function CallsC.7 Control-Flow StatementsSummaryC.8 More Data TypesSummaryC.9 Standard LibrariesC.10 Compiler and Command Line OptionsC.11 Common Mistakes

Content preview from Digital Design and Computer Architecture, ARM Edition

Table 6.10

Index mode control bits for memory instructions

P	W	Index Mode
0	0	Post-index
0	1	Not supported
1	0	Offset
1	1	Pre-index

Table 6.11

Memory operation type control bits for memory instructions

L	B	Instruction
0	0	STR
0	1	STRB
1	0	LDR
1	1	LDRB

Example 6.3

Translating Memory Instructions into Machine Language

Translate the following assembly language statement into machine language.

STR R11, [R5], #-26

Solution

STR is a memory instruction, so it has an op of 01₂. According to Table 6.11, L = 0 and B = 0 for STR. The instruction uses post-indexing, so according to Table 6.10, P = 0 and W = 0. The immediate offset is subtracted from the base, so $\bar{I} = 0$ and U = 0.