June 2025
Intermediate to advanced
400 pages
10h 37m
English
book
Distributed Time-Sensitive Systems
by Tanupriya Choudhury, Rahul Kumar Singh, Ravi Tomar, S. Balamurugan, J. C. Patni
Content preview from Distributed Time-Sensitive Systems
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3Implementation of High Speed Adders for Image Blending Applications
P. Vanjipriya1*, K. N. Vijeyakumar1, E. Udayakumar2 and S. Vishnushree1
1Dept. of ECE, Dr. Mahalingam College of Engineering and Technology, Pollachi, Tamil Nadu, India
2Dept. of ECE, KIT-Kalaignarkarunanidhi Institute of Technology, Coimbatore, Tamil Nadu, India
Abstract
The adder is a core component of the central processing unit (CPU), Digital Signal Processors, image de-noising filters. The performance of the system as a whole depends on tradeoff between power dissipation, area and speed of the adder used. The speed of the addition operation is constrained by propagation of carry signal from least to most significant bit weights in a multi-bit addition. Parallel prefix adders (PPA) offer the best delay performance and more suitable for high-speed applications. In this work, a performance evaluation of various adder designs viz., CarrySelectAdder (CSLA), Carry lookahead adder (CLA), and KoggeStoneAdder (KSA) is made. The suggested adder algorithms are created using Cadence Encounter with 90nm CMOS PDK technology and structural verilog HDL modeling. Simulations reveal that the CSLA design fair 24.36% and 41.89% area reductions, 23.1% and 39.455% power reductions when compared with CLA and KS adders, respectively, for an 8-bit implementation. Contrarily, KS adder fair 64.94% and 56.43% delay reductions when compared with CSLA and CLA designs.
Keywords: CSLA, CLA, PPA, CMOS PDK technology, image blending ...
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