February 2020
Intermediate
146 pages
3h 54m
English
Content preview from Durable Phase-Change Memory Architectures
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Chapter Four
Inter-line level schemes for handling hard errors in PCMs
Marjan Asadiniaa; Hamid Sarbazi-Azadb azad@sharif.edu a University of Arkansas, Fayetteville, AR, United Statesb Sharif University of Technology and Institute for Research in Fundamental Sciences (IPM), Tehran, Iran
Abstract
To address the problem of fast degradation in PCM main memory systems in the presence of severe cell wear-out, this chapter introduces and evaluates some ways to deal with hard error issues in phase change memory. Our observation reveals when some memory pages reach their endurance limits, other pages may be far from their limits even when using a perfect wear-leveling. Recent studies have proposed redirection or correction schemes to alleviate ...
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