Model-based Design for Heterogeneous FPGA

11.1 Introduction

The material to this point has clearly indicated the requirement for a shift toward higher-level representations of FPGA-based DSP systems and the need for carrying out optimizations at this higher level. The material in Chapter 6 covered lower-level design techniques which were aimed at producing efficient FPGA implementations of circuit architectures. These design techniques covered not only the choice of how to map memory requirements into LUT and embedded RAM resources and the implications that this has on performance, but also the use of distributed arithmetic and reconfigurable multiplexers to reduce hardware costs. However, the evolution of FPGA technologies toward coarser-grained heterogeneous platforms, i.e. those comprising processors and complex DSP blocks involving dedicated multipliers and MAC units, has negated the impact of many of these latter techniques.

The material in Chapter 8 and the subsequent tool development work in Chapter 9, showed how it is possible to explore levels of parallelism and pipelining at SFG and DFG descriptions of DSP system, rather than at the lower-level HDL-based circuit architecture. It was shown how levels of parallelism and pipelining could be adjusted to best match the performance requirement of the application under consideration against the processing and memory resources of the FPGA technology available. This assumes that the SFG representation effectively represents ...

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