FPGA-based Implementation of Signal Processing Systems, 2nd Edition

9 Complex DSP Core Design for FPGA

9.1 Introduction

It is feasible to incorporate many billions of gates on a single chip, permitting extremely complex functions to be built as a complete SoC. This offers advantages of lower power, greater reliability and reduced cost of manufacture and has enabled an expansion of FPGA capabilities with devices such as Altera’s Stratix^® 10 and Xilinx’s UltraScale^TM FPGA families. With their vast expanse of usable logic comes the problem of implementing increasingly complex systems on these devices.

This problem has been coined the “design productivity gap” (ITRS 1999) and has increasingly become of major concern within the electronics industry. Whilst Moore’s law predicts that the number of available transistors will grow at a 58% annual growth rate, there will only be a 21% annual growth rate in design productivity. This highlights a divergence that will not be closed by incremental improvements in design productivity. Instead a complete shift in the methodology of designing and implementing multi-million-gate chips is needed that will allow designers to concentrate on higher levels of abstraction within the designs.

As the silicon density increases, the design complexity increases at a far greater rate since silicon systems are now composed of more facets of the full system design and may combine components from a range of technological disciplines. Working more at the system level, designers become more heavily involved with integrating ...