GNU Autoconf, Automake, and Libtool

3.3. Macros

You can use a number of helpful macros anywhere throughout the 'Makefile'. Macros start with a dollar sign, like shell variables. Our first 'Makefile' example used a few:

$(CC) $(CFLAGS) -c $< -o $@

Here, syntactic forms of '$(..)' are make variable expansions. You can define a make variable using a 'VAR=VALUE' syntax, as follows:

CC=ec++

In a 'Makefile', $(CC) is then literally replaced by 'ec++'. make has a number of built-in variables and default values. The default value for $(CC) is 'cc'.

Other built-in macros exist with fixed semantics. The two most common macros are $@ and $<. They represent the names of the target and the first dependency for the rule in which they appear. Here is a simple Makefile:

 all: dummy @echo "$@ ...