System on Chip (SoC) Design and Test
Abstract
With the advent of system on chip (SoC), the issues related to design, verification, debug, and testing of SoCs have become more complex and challenging compared with those of a single block or an intellectual property (IP) core. This chapter first introduces the background on very large scale integration (VLSI) testing and the IP-based SoC lifecycle, then briefly discusses the issues associated with design, verification, debug, and test at the SoC level. Thereafter, methodologies for design-for-debug and design-for-testability are presented in this chapter.
Keywords
System on Chip; IP Reuse; Verification; Design-for-Debug; Design-for-Testability
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