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High Performance Parallelism Pearls Volume One by James Jeffers, James Reinders

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Chapter 5

Plesiochronous Phasing Barriers

Jim Dempsey    QuickThread Programming, LLC, USA

Abstract

This chapter clearly illustrates that by using a little bit of ingenuity and, for now, slightly different programming technique, that for a program like the referenced HPP Chapter 4 program, optimized by perhaps the best programmers at Intel, can be bested by an additional 40-50% in performance. Please note, those programmers are likely much better that I am at program optimization, I merely saw an opportunity they missed.

Keywords

Plesiochronous

Thread synchronization

Hyper-threads

Hardware threads

Barrier

Diffusion

Cache hit

Cache locality

Peel

In telecommunications, a plesiochronous system is one where different parts of the system are almost, ...

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