January 2004
Intermediate to advanced
432 pages
11h 1m
English
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List of Figures
Figure 1-1 Processor Block Diagram
Figure 1-2 32-Bit General Registers
Figure 1-3 64-Bit General Registers
Figure 1-4 Control Registers
Figure 1-5 32-Bit Address Space Layout
Figure 1-6 64-Bit Address Space Layout
Figure 1-7 Address Swizzling
Figure 1-8 Translation of Virtual Address to Physical Address
Figure 1-9 Address Translation through the TLB and Cache
Figure 2-1 Stack Usage in Narrow Mode
Figure 2-2 Stack Usage in Wide Mode
Figure 2-3 Stack Usage for the Call to proc()
Figure 3-1 The Big Picture
Figure 3-2 Virtual Memory Objects, Private and Shared
Figure 3-3 Tables and Lists
Figure 3-4 Resource Maps
Figure 3-5 Hashtables and Chains
Figure 3-6 Partitioned Tables
Figure 3-7 B-Trees
Figure 3-8 Sparse Tables