Chapter 11. Describing System-Level Parallelism

In the preceding chapters, we have focused primarily on the creation of individual processes and described how these processes may be optimized for performance using techniques such as array splitting, loop pipelining, and loop unrolling. We have also seen how additional processes may be used for the purpose of testing by creating both desktop and embedded software test benches that interact with Impulse C hardware processes during simulation or during actual operation within an FPGA.

In this chapter, we will return to the topic of communicating processes and show how the use of system-level parallelism can improve throughput for many types of applications. Applications designed in this way might ...

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