book

Principles of Power Integrity for PDN Design--Simplified: Robust and Cost Effective Design for High Speed Digital Products

by Eric Bogatin, Larry D. Smith

March 2017

Intermediate to advanced

816 pages

18h 20m

English

Pearson

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1.1 What Is the Power Delivery Network (PDN) and Why Should I Care?1.2 Engineering the PDN1.3 “Working” or “Robust” PDN Design1.4 Sculpting the PDN Impedance Profile1.5 The Bottom LineReference
2.1 Why Do We Care About Impedance?2.2 Impedance in the Frequency Domain2.3 Calculating or Simulating Impedance2.4 Real Circuit Components vs. Ideal Circuit Elements2.5 The Series RLC Circuit2.6 The Parallel RLC Circuit2.7 The Resonant Properties of a Series and Parallel RLC Circuit2.8 Examples of RLC Circuits and Real Capacitors2.9 The PDN as Viewed by the Chip or by the Board2.10 Transient Response2.11 Advanced Topic: The Impedance Matrix2.12 The Bottom LineReferences

3.1 Why Do We Care About Measuring Low Impedance?3.2 Measurements Based on the V/I Definition of Impedance3.3 Measuring Impedance Based on the Reflection of Signals3.4 Measuring Impedance with a VNA3.5 Example: Measuring the Impedance of Two Leads in a DIP3.6 Example: Measuring the Impedance of a Small Wire Loop3.7 Limitations of VNA Impedance Measurements at Low Frequency3.8 The Four-Point Kelvin Resistance Measurement Technique3.9 The Two-Port Low Impedance Measurement Technique3.10 Example: Measuring the Impedance of a 1-inch Diameter Copper Loop3.11 Accounting for Fixture Artifacts3.12 Example: Measured Inductance of a Via3.13 Example: Small MLCC Capacitor on a Board3.14 Advanced Topic: Measuring On-Die Capacitance3.15 The Bottom LineReferences
4.1 Why Do We Care About Inductance in PDN Design?4.2 A Brief Review of Capacitance to Put Inductance in Perspective4.3 What Is Inductance? Essential Principles of Magnetic Fields and Inductance4.4 Impedance of an Inductor4.5 The Quasi-Static Approximation for Inductance4.6 Magnetic Field Density, B4.7 Inductance and Energy in the Magnetic Field4.8 Maxwell’s Equations and Loop Inductance4.9 Internal and External Inductance and Skin Depth4.10 Loop and Partial, Self- and Mutual Inductance4.11 Uniform Round Conductors4.12 Approximations for the Loop Inductance of Round Loops4.13 Loop Inductance of Wide Conductors Close Together4.14 Approximations for the Loop Inductance of Any Uniform Transmission Line4.15 A Simple Rule of Thumb for Loop Inductance4.16 Advanced Topic: Extracting Loop Inductance from the S-parameters Calculated with a 3D Field Solver4.17 The Bottom LineReferences
5.1 Why Use Capacitors?5.2 Equivalent Circuit Models for Real Capacitors5.3 Combining Multiple Identical Capacitors in Parallel5.4 The Parallel Resonance Frequency Between Two Different Capacitors5.5 The Peak Impedance at the PRF5.6 Engineering the Capacitance of a Capacitor5.7 Capacitor Temperature and Voltage Stability5.8 How Much Capacitance Is Enough?5.9 The ESR of Real Capacitors: First- and Second-Order Models5.10 Estimating the ESR of Capacitors from Spec Sheets5.11 Controlled ESR Capacitors5.12 Mounting Inductance of a Capacitor5.13 Using Vendor-Supplied S-parameter Capacitor Models5.14 How to Analyze Vendor-Supplied S-Parameter Models5.15 Advanced Topics: A Higher Bandwidth Capacitor Model5.16 The Bottom LineReferences
6.1 The Key Role of Planes6.2 Low-Frequency Property of Planes: Parallel Plate Capacitance6.3 Low-Frequency Property of Planes: Fringe Field Capacitance6.4 Low-Frequency Property of Planes: Fringe Field Capacitance in Power Puddles6.5 Loop Inductance of Long, Narrow Cavities6.6 Spreading Inductance in Wide Cavities6.7 Extracting Spreading Inductance from a 3D Field Solver6.8 Lumped-Circuit Series and Parallel Self-Resonant Frequency6.9 Exploring the Features of the Series LC Resonance6.10 Spreading Inductance and Source Contact Location6.11 Spreading Inductance Between Two Contact Points6.12 The Interactions of a Capacitor and Cavities6.13 The Role of Spreading Inductance: When Does Capacitor Location Matter?6.14 Saturating the Spreading Inductance6.15 Cavity Modal Resonances and Transmission Line Properties6.16 Input Impedance of a Transmission Line and Modal Resonances6.17 Modal Resonances and Attenuation6.18 Cavity Modes in Two Dimensions6.19 Advanced Topic: Using Transfer Impedance to Probe Spreading Inductance6.20 The Bottom LineReferences
7.1 Signal Integrity and Planes7.2 Why the Peak Impedances Matter7.3 Reducing Cavity Noise through Lower Impedance and Higher Damping7.4 Suppressing Cavity Resonances with Shorting Vias7.5 Suppressing Cavity Resonances with Many DC Blocking Capacitors7.6 Estimating the Number of DC Blocking Capacitors to Suppress Cavity Resonances7.7 Determining How Many DC Blocking Capacitors Are Needed to Carry Return Current7.8 Cavity Impedance with a Suboptimal Number of DC Blocking Capacitors7.9 Spreading Inductance and Capacitor Mounting Inductance7.10 Using Damping to Suppress Parallel Resonant Peaks Created by a Few Capacitors7.11 Cavity Losses and Impedance Peak Reduction7.12 Using Multiple Capacitor Values to Suppress Impedance Peak7.13 Using Controlled ESR Capacitors to Reduce Peak Impedance Heights7.14 Summary of the Most Important Design Principles for Managing Return Planes7.15 Advanced Topic: Modeling Planes with Transmission Line Circuits7.16 The Bottom LineReferences
8.1 Putting the Elements Together: The PDN Ecology and the Frequency Domain8.2 At the High-Frequency End: The On-Die Decoupling Capacitance8.3 The Package PDN8.4 The Bandini Mountain8.5 Estimating the Typical Bandini Mountain Frequency8.6 Intrinsic Damping of the Bandini Mountain8.7 The Power Ground Planes with Multiple Via Pair Contacts8.8 Looking from the Chip Through the Package into the PCB Cavity8.9 Role of the Cavity: Small Boards, Large Boards, and “Power Puddles”8.10 At the Low Frequency: The VRM and Its Bulk Capacitor8.11 Bulk Capacitors: How Much Capacitance Is Enough?8.12 Optimizing the Bulk Capacitor and VRM8.13 Building the PDN Ecosystem: The VRM, Bulk Capacitor, Cavity, Package, and On-Die Capacitance8.14 The Fundamental Limits to the Peak Impedance8.15 Using One Value MLCC Capacitor on the Board-General Features8.16 Optimizing the Single MLCC Capacitance Value8.17 Using Three Different Values of MLCC Capacitors on the Board8.18 Optimizing the Values of Three Capacitors8.19 The Frequency Domain Target Impedance Method (FDTIM) for Selecting Capacitor Values and the Minimum Number of Capacitors8.20 Selecting Capacitor Values with the FDTIM8.21 When the On-Die Capacitance Is Large and Package Lead Inductance Is Small8.22 An Alternative Decoupling Strategy Using Controlled ESR Capacitors8.23 On-Package Decoupling (OPD) Capacitors8.24 Advanced Section: Impact of Multiple Chips on the Board Sharing the Same Rail8.25 The Bottom LineReferences
9.1 What’s So Important About the Transient Current?9.2 A Flat Impedance Profile, a Transient Current, and a Target Impedance9.3 Estimating the Transient Current to Calculate the Target Impedance with a Flat Impedance Profile9.4 The Actual PDN Current Profile Through a Die9.5 Clock-Edge Current When Capacitance Is Referenced to Both Vss and Vdd9.6 Measurement Example: Embedded Controller Processor9.7 The Real Origin of PDN Noise–How Clock-Edge Current Drives PDN Noise9.8 Equations That Govern a PDN Impedance Peak9.9 The Most Important Current Waveforms That Characterize the PDN9.10 PDN Response to an Impulse of Dynamic Current9.11 PDN Response to a Step Change in Dynamic Current9.12 PDN Response to a Square Wave of Dynamic Current at Resonance9.13 Target Impedance and the Transient and AC Steady-State Responses9.14 Impact of Reactive Elements, q-Factor, and Peak Impedances on PDN Voltage Noise9.15 Rogue Waves9.16 A Robust Design Strategy in the Presence of Rogue Waves9.17 Clock-Edge Current Impulses from Switched Capacitor Loads9.18 Transient Current Waveforms Composed of a Series of Clock Impulses9.19 Advanced Section: Applying Clock Gating, Clock Swallowing, and Power Gating to Real CMOS Situations9.20 Advanced Section: Power Gating9.21 The Bottom LineReferences
10.1 Reiterating Our Goal in PDN Design10.2 Summary of the Most Important Power Integrity Principles10.3 Introducing a Spreadsheet to Explore Design Space10.4 Lines 1–12: PDN Input Voltage, Current, and Target Impedance Parameters10.5 Lines 13–24: 0th Dip (Clock-Edge) Noise and On-Die Parameters10.6 Extracting the Mounting Inductance and Resistance10.7 Analyzing Typical Board and Package Geometries for Inductance10.8 The Three Loops of the PDN Resonance Calculator (PRC) Spreadsheet10.9 The Performance Figures of Merit10.10 Significance of Damping and q-factors10.11 Using a Switched Capacitor Load Model to Stimulate the PDN10.12 Impulse, Step, and Resonance Response for Three-Peak PDN: Correlation to Transient Simulation10.13 Individual q-factors in Both the Frequency and Time Domains10.14 Rise Time and Stimulation of Impedance Peak10.15 Improvements for a Three-Peak PDN: Reduced Loop Inductance of the Bandini Mountain and Selective MLCC Capacitor Values10.16 Improvements for a Three-Peak PDN: A Better SMPS Model10.17 Improvements for a Three-Peak PDN: On-Package Decoupling (OPD) Capacitors10.18 Transient Response of the PDN: Before and After Improvement10.19 Re-examining Transient Current Assumptions10.20 Practical Limitations: Risk, Performance, and Cost Tradeoffs10.21 Reverse Engineering the PDN Features from Measurements10.22 Simulation-to-Measurement Correlation10.23 Summary of the Simulated and Measured PDN Impedance and Voltage Features10.24 The Bottom LineReferences

Content preview from Principles of Power Integrity for PDN Design--Simplified: Robust and Cost Effective Design for High Speed Digital Products

Principles of Power Integrity for PDN Design—Simplified

Robust and Cost Effective Design for High Speed Digital Products

Larry D. SmithEric Bogatin

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