Cores and Intellectual Property
13.1 Overview
FPGA intellectual property (IP) can be defined as a reusable design block (hard, firm or soft) with a fixed-range of functionality. The term IP usually refers to a pre-verified functional design block that is obtained from a group outside the local design team. An exception to this can occur when a design block is being incorporated from a different in-house project. Also, IP usually implies some level of previous testing, although this is not an absolute requirement. Available IP offerings cover a wide range of design applications and functionality. Common terms used to describe IP blocks include library parameterized modules (LPMs), megafunctions, macros, relationally placed macros ...
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