book

RTL Hardware Design Using VHDL: Coding for Efficiency, Portability, and Scalability

Name: RTL Hardware Design Using VHDL: Coding for Efficiency, Portability, and Scalability
Author: Pong P. Chu
ISBN: 9780471720928

by Pong P. Chu

April 2006

Intermediate to advanced

694 pages

19h 36m

English

Wiley-IEEE Press

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Cover Page
Title Page
Copyright
Dedication
CONTENTS
PREFACE
ACKNOWLEDGMENTS
CHAPTER 1: INTRODUCTION TO DIGITAL SYSTEM DESIGN
1.1 INTRODUCTION1.2 DEVICE TECHNOLOGIES1.3 SYSTEM REPRESENTATION1.4 LEVELS OF ABSTRACTION1.5 DEVELOPMENT TASKS AND EDA SOFTWARE1.6 DEVELOPMENT FLOW1.7 OVERVIEW OF THE BOOK1.8 BIBLIOGRAPHIC NOTESProblems
CHAPTER 2: OVERVIEW OF HARDWARE DESCRIPTION LANGUAGES
2.1 HARDWARE DESCRIPTION LANGUAGES2.2 BASIC VHDL CONCEPT VIA AN EXAMPLE2.3 VHDL IN DEVELOPMENT FLOW2.4 BIBLIOGRAPHIC NOTESProblems
CHAPTER 3: BASIC LANGUAGE CONSTRUCTS OF VHDL
3.1 INTRODUCTION3.2 SKELETON OF A BASIC VHDL PROGRAM3.3 LEXICAL ELEMENTS AND PROGRAM FORMAT3.4 OBJECTS3.5 DATA TYPES AND OPERATORS3.6 SYNTHESIS GUIDELINES3.7 BIBLIOGRAPHIC NOTESProblems

CHAPTER 4: CONCURRENT SIGNAL ASSIGNMENT STATEMENTS OF VHDL
4.1 COMBINATIONAL VERSUS SEQUENTIAL CIRCUITS4.2 SIMPLE SIGNAL ASSIGNMENT STATEMENT4.3 CONDITIONAL SIGNAL ASSIGNMENT STATEMENT4.4 SELECTED SIGNAL ASSIGNMENT STATEMENT4.5 CONDITIONAL SIGNAL ASSIGNMENT STATEMENT VERSUS SELECTED SIGNAL ASSIGNMENT STATEMENT4.6 SYNTHESIS GUIDELINES4.7 BIBLIOGRAPHIC NOTESProblems
CHAPTER 5: SEQUENTIAL STATEMENTS OF VHDL
5.1 VHDL PROCESS5.2 SEQUENTIAL SIGNAL ASSIGNMENT STATEMENT5.3 VARIABLE ASSIGNMENT STATEMENT5.4 IF STATEMENT5.5 CASE STATEMENT5.6 SIMPLE FOR LOOP STATEMENT5.7 SYNTHESIS OF SEQUENTIAL STATEMENTS5.8 SYNTHESIS GUIDELINES5.9 BIBLIOGRAPHIC NOTESProblems
CHAPTER 6: SYNTHESIS OF VHDL CODE
6.1 FUNDAMENTAL LIMITATIONS OF EDA SOFTWARE6.2 REALIZATION OF VHDL OPERATORS6.3 REALIZATION OF VHDL DATA TYPES6.4 VHDL SYNTHESIS FLOW6.5 TIMING CONSIDERATIONS6.6 SYNTHESIS GUIDELINES6.7 BIBLIOGRAPHIC NOTESProblems
CHAPTER 7: COMBINATIONAL CIRCUIT DESIGN: PRACTICE
7.1 DERIVATION OF EFFICIENT HDL DESCRIPTION7.2 OPERATOR SHARING7.3 FUNCTIONALITY SHARING7.4 LAYOUT-RELATED CIRCUITS7.5 GENERAL CIRCUITS7.6 SYNTHESIS GUIDELINES7.7 BIBLIOGRAPHIC NOTESProblems
CHAPTER 8: SEQUENTIAL CIRCUIT DESIGN: PRINCIPLE
8.1 OVERVIEW OF SEQUENTIAL CIRCUITS8.2 SYNCHRONOUS CIRCUITS8.3 DANGER OF SYNTHESIS THAT USES PRIMITIVE GATES8.4 INFERENCE OF BASIC MEMORY ELEMENTS8.5 SIMPLE DESIGN EXAMPLES8.6 TIMING ANALYSIS OF A SYNCHRONOUS SEQUENTIAL CIRCUIT8.7 ALTERNATIVE ONE-SEGMENT CODING STYLE8.8 USE OF VARIABLES IN SEQUENTIAL CIRCUIT DESCRIPTION8.9 SYNTHESIS OF SEQUENTIAL CIRCUITS8.10 SYNTHESIS GUIDELINES8.11 BIBLIOGRAPHIC NOTESProblems
CHAPTER 9: SEQUENTIAL CIRCUIT DESIGN: PRACTICE
9.1 POOR DESIGN PRACTICES AND THEIR REMEDIES9.2 COUNTERS9.3 REGISTERS AS TEMPORARY STORAGE9.4 PIPELINED DESIGN9.5 SYNTHESIS GUIDELINES9.6 BIBLIOGRAPHIC NOTESProblems
CHAPTER 10: FINITE STATE MACHINE: PRINCIPLE AND PRACTICE
10.1 OVERVIEW OF FSMS10.2 FSM REPRESENTATION10.3 TIMING AND PERFORMANCE OF AN FSM10.4 MOORE MACHINE VERSUS MEALY MACHINE10.5 VHDL DESCRIPTION OF AN FSM10.6 STATE ASSIGNMENT10.7 MOORE OUTPUT BUFFERING10.8 FSM DESIGN EXAMPLES10.9 BIBLIOGRAPHIC NOTESProblems
CHAPTER 11: REGISTER TRANSFER METHODOLOGY: PRINCIPLE
11.1 INTRODUCTION11.2 OVERVIEW OF FSMD11.3 FSMD DESIGN OF A REPETITIVE-ADDITION MULTIPLIER11.4 ALTERNATIVE DESIGN OF A REPETITIVE-ADDITION MULTIPLIER11.5 TIMING AND PERFORMANCE ANALYSIS OF FSMD11.6 SEQUENTIAL ADD-AND-SHIFT MULTIPLIER11.7 SYNTHESIS OF FSMD11.8 SYNTHESIS GUIDELINES11.9 BIBLIOGRAPHIC NOTESProblems
CHAPTER 12: REGISTER TRANSFER METHODOLOGY: PRACTICE
12.1 INTRODUCTION12.2 ONE-SHOT PULSE GENERATOR12.3 SRAM CONTROLLER12.4 GCD CIRCUIT12.5 UART RECEIVER12.6 SQUARE-ROOT APPROXIMATION CIRCUIT12.7 HIGH-LEVEL SYNTHESIS12.8 BIBLIOGRAPHIC NOTESProblems
CHAPTER 13: HIERARCHICAL DESIGN IN VHDL
13.1 INTRODUCTION13.2 COMPONENTS13.3 GENERICS13.4 CONFIGURATION13.5 OTHER SUPPORTING CONSTRUCTS FOR A LARGE SYSTEM13.6 PARTITION13.7 SYNTHESIS GUIDELINES13.8 BIBLIOGRAPHIC NOTESProblems
CHAPTER 14: PARAMETERIZED DESIGN: PRINCIPLE
14.1 INTRODUCTION14.2 TYPES OF PARAMETERS14.3 SPECIFYING PARAMETERS14.4 CLEVER USE OF AN ARRAY14.5 FOR GENERATE STATEMENT14.6 CONDITIONAL GENERATE STATEMENT14.7 FOR LOOP STATEMENT14.8 EXIT AND NEXT STATEMENTS14.9 SYNTHESIS OF ITERATIVE STRUCTURE14.10 SYNTHESIS GUIDELINES14.11 BIBLIOGRAPHIC NOTESProblems
CHAPTER 15: PARAMETERIZED DESIGN: PRACTICE
15.1 INTRODUCTION15.2 DATA TYPES FOR TWO-DIMENSIONAL SIGNALS15.3 COMMONLY USED INTERMEDIATE-SIZED RT-LEVEL COMPONENTS15.4 MORE SOPHISTICATED EXAMPLES15.5 SYNTHESIS OF PARAMETERIZED MODULES15.6 SYNTHESIS GUIDELINES15.7 BIBLIOGRAPHIC NOTESProblems
CHAPTER 16: CLOCK AND SYNCHRONIZATION: PRINCIPLE AND PRACTICE
16.1 OVERVIEW OF A CLOCK DISTRIBUTION NETWORK16.2 TIMING ANALYSIS WITH CLOCK SKEW16.3 OVERVIEW OF A MULTIPLE-CLOCK SYSTEM16.4 METASTABILITY AND SYNCHRONIZATION FAILURE16.5 BASIC SYNCHRONIZER16.6 SINGLE ENABLE SIGNAL CROSSING CLOCK DOMAINS16.7 HANDSHAKING PROTOCOL16.8 DATA TRANSFER CROSSING CLOCK DOMAINS16.9 DATA TRANSFER VIA A MEMORY BUFFER16.10 SYNTHESIS OF A MULTIPLE-CLOCK SYSTEM16.11 SYNTHESIS GUIDELINES16.12 BIBLIOGRAPHIC NOTESProblems
REFERENCES
INDEX

Content preview from RTL Hardware Design Using VHDL: Coding for Efficiency, Portability, and Scalability

CHAPTER 9 SEQUENTIAL CIRCUIT DESIGN: PRACTICE

After learning the basic model and coding style, we explore more sophisticated regular sequential circuits in this chapter. The design examples show the implementation of a variety of counters, the use of registers as fast, temporary storage, and the construction of a “pipeline” to increase the throughput of certain combinational circuits.

9.1 POOR DESIGN PRACTICES AND THEIR REMEDIES

Synchronous design is the most important design methodology for developing a large, complex, reliable digital system. In the past, some poor, non-synchronous design practices were used. Those techniques failed to follow the synchronous principle and should be avoided in RT-level design. Before continuing with more examples, we examine those practices and their remedies. The most common problems are:

Misuse of the asynchronous reset.
Misuse of the gated clock.
Misuse of the derived clock.

Some of those practices were used when a system was realized by SSI and MSI devices and the silicon real estate and printed circuit board were a premium. Designers tended to cut corners to save a few chips. These legacy practices are no longer applicable in today's design environment and should be avoided. The following subsections show how to remedy these poor non-synchronous design practices.

Figure 9.1 Decade counter using asynchronous reset.

In few special situations, ...

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RTL Hardware Design Using VHDL: Coding for Efficiency, Portability, and Scalability

by Pong P. Chu

CHAPTER 9

SEQUENTIAL CIRCUIT DESIGN: PRACTICE

9.1 POOR DESIGN PRACTICES AND THEIR REMEDIES

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