book

Verilog Coding for Logic Synthesis

Name: Verilog Coding for Logic Synthesis
Author: Weng Fook Lee
ISBN: 9780471429760

by Weng Fook Lee

April 2003

Intermediate to advanced

336 pages

6h 39m

English

Wiley-Interscience

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Cover Page
Title Page
Copyright
Dedication
Contents
Table of Figures
Table Of Examples
List Of Tables
Preface
Acknowledgments

Trademarks
CHAPTER ONE: Introduction
CHAPTER TWO: ASIC Design Flow
2.1 SPECIFICATION2.2 RTL CODING2.3 TEST BENCH AND SIMULATION2.4 SYNTHESIS2.5 PRE-LAYOUT TIMING ANALYSIS2.6 APR2.7 BACK ANNOTATION2.8 POST-LAYOUT TIMING ANALYSIS2.9 LOGIC VERIFICATION
CHAPTER THREE: Verilog Coding
3.1 INTRODUCTION TO BASIC VERILOG CONCEPTS3.2 VERILOG GATE-LEVEL PRIMITIVES3.3 USER-DEFINED PRIMITIVES3.4 CONCURRENT AND SEQUENTIAL STATEMENTS
CHAPTER FOUR: Coding Style: Best-Known Method for Synthesis
4.1 NAMING CONVENTION4.2 DESIGN PARTITIONING4.3 CLOCK4.4 RESET4.5 TIMING LOOP4.6 BLOCKING AND NONBLOCKING STATEMENTS4.7 SENSITIVITY LIST4.8 VERILOG OPERATORS4.9 LATCH INFERENCE4.10 MEMORY ARRAY4.11 STATE MACHINE DESIGN
CHAPTER FIVE: Design Example of Programmable Timer
5.1 PROGRAMMABLE TIMER DESIGN SPECIFICATION5.2 MICROARCHITECTURE DEFINITION FOR PROGRAMMABLE TIMER5.3 FLOW DIAGRAM DEFINITION FOR PROGRAMMABLE TIMER5.4 VERILOG CODE FOR PROGRAMMABLE TIMER5.5 SYNTHESIZABLE VERILOG CODE FOR PROGRAMMABLE TIMER
CHAPTER SIX: Design Example of Programmable Logic Block for Peripheral Interface
6.1 PROGRAMMABLE LOGIC BLOCK FOR PERIPHERAL INTERFACE DESIGN SPECIFICATION6.2 MODE OF OPERATION FOR PROGRAMMABLE LOGIC BLOCK FOR PERIPHERAL INTERFACE6.3 MICRO-ARCHITECTURE DEFINITION FOR PROGRAMMABLE PERIPHERAL INTERFACE6.4 FLOW DIAGRAM DEFINITION FOR PROGRAMMABLE PERIPHERAL INTERFACE6.5 SYNTHESIZABLE VERILOG CODE FOR PROGRAMMABLE PERIPHERAL INTERFACE6.6 SIMULATION FOR PROGRAMMABLE PERIPHERAL INTERFACE DESIGN
Appendix
APPENDIX A.1 TWO-BIT BY TWO-BIT ADDERAPPENDIX A.2 TWO-BIT BY TWO-BIT SUBTRACTORAPPENDIX A.3 FOUR-BIT BY FOUR-BIT MULTIPLIER
Glossary
Bibliography
Index

Overview

Provides a practical approach to Verilog design and problem solving.

Bulk of the book deals with practical design problems that design engineers solve on a daily basis.
Includes over 90 design examples.
There are 3 full scale design examples that include specification, architectural definition, micro-architectural definition, RTL coding, testbench coding and verification.
Book is suitable for use as a textbook in EE departments that have VLSI courses

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