RTL Hardware Design Using VHDL: Coding for Efficiency, Portability, and Scalability
by Pong P. Chu
INDEX
abstraction, 9
gate-level, 10
processor-level, 12
register-transfer (RT) level, 11
transistor-level, 10
actual signal, 478
alias, 52
arbiter, 353
array
aggregate, 59
array-of-arrays, 548
constrained, 546
emulated two-dimensional, 550
two-dimensional, 546
ASIC, 3
full custom, 3
gate array, 3
ASM chart, 317
ASMD chart, 379
association
named, 479
positional, 480
asynchronous circuit, 216, 219
attribute
'event, 222
'high, 502
'left, 502
'length, 502
'low, 502
'range, 502
'reverse_range, 502
'right, 502
array, 502
enum_encoding, 339
user, 339
bidirectional I/O, 134
big-O notation, 126
binary decoder, 73, 86, 104, 112, 513, 528, 558
binary encoder, 564
binding, 461
CAM (content addressable memory), 287
case statement, 112
clock
distribution network, 603
gated, 260
skew, 605
combinational circuit, 69, 213
comment, 47
computability, 126
computation complexity, 126
concurrent statement, 46
conditional signal assignment statement, 72, 105
configuration, 37, 46, 485, 526
declaration, 486
specification, 488
constant, 52
cost
development, 7
non-recurring engineering (NRE), 6
part, 6
time-to-market, 7
counter
arbitrary-sequence, 232
binary, 233, 247, 367, 482, 518, 521
Gray, 265
mod-n, 483
programmable, 237
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