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RTL Hardware Design Using VHDL: Coding for Efficiency, Portability, and Scalability
book

RTL Hardware Design Using VHDL: Coding for Efficiency, Portability, and Scalability

by Pong P. Chu
April 2006
Intermediate to advanced
694 pages
19h 36m
English
Wiley-IEEE Press
Content preview from RTL Hardware Design Using VHDL: Coding for Efficiency, Portability, and Scalability

INDEX

abstraction, 9

gate-level, 10

processor-level, 12

register-transfer (RT) level, 11

transistor-level, 10

actual signal, 478

adder, 171, 201, 510

alias, 52

ALU, 75, 87, 104, 112

arbiter, 353

architecture body, 28, 46

array

aggregate, 59

array-of-arrays, 548

constrained, 546

emulated two-dimensional, 550

two-dimensional, 546

unconstrained, 503, 547

ASIC, 3

full custom, 3

gate array, 3

standard-cell, 3, 143

ASM chart, 317

ASMD chart, 379

association

named, 479

positional, 480

asynchronous circuit, 216, 219

attribute

'event, 222

'high, 502

'left, 502

'length, 502

'low, 502

'range, 502

'reverse_range, 502

'right, 502

array, 502

enum_encoding, 339

user, 339

barrel shifter, 178, 192, 566

bidirectional I/O, 134

big-O notation, 126

binary decoder, 73, 86, 104, 112, 513, 528, 558

binary encoder, 564

binding, 461

CAM (content addressable memory), 287

case statement, 112

clock

derived, 262, 611

distribution network, 603

gated, 260

skew, 605

combinational circuit, 69, 213

comment, 47

comparator, 173, 177

component, 30, 475

declaration, 31, 475

instantiation, 32, 477

computability, 126

computation complexity, 126

concurrent statement, 46

conditional signal assignment statement, 72, 105

configuration, 37, 46, 485, 526

declaration, 486

specification, 488

constant, 52

cost

development, 7

non-recurring engineering (NRE), 6

part, 6

time-to-market, 7

counter

arbitrary-sequence, 232

binary, 233, 247, 367, 482, 518, 521

decade, 236, 476

decimal, 272, 481

Gray, 265

mod-n, 483

programmable, 237

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