Scalable Shared-Memory Multiprocessing

5.3 Reflective Memory Systems ^ 157

node on the same ring is 7.5 μs (150 cycles). When a cache miss occurs in one node, and the

memory is actuaUy found on another ring, several directory lookups have to be accomplished

before the data is found and can be passed back. The latency for this kind of miss is as long

as 28.5 μs (570 cycles). For the KSR-2, doubhng the speed of the processors further

increases memory latencies in terms of processor cycles.

5.3 Reflective Memory Systems

Reflective memory systems attempt to minimize the processor stalls caused by read misses

by satisfying aU read misses from a local copy of shared memory. Shared memor ...