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See MIPS Run, 2nd Edition

Name: See MIPS Run, 2nd Edition
Author: Dominic Sweetman
ISBN: 9780080525235

by Dominic Sweetman

July 2010

Intermediate to advanced

512 pages

14h 2m

English

Morgan Kaufmann

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Cover
Title Page
Copyright
Foreword
Preface
Style and LimitsConventionsAcknowledgments
Table of Contents
Chapter 1: RISCs and MIPS Architectures
1.1 Pipelines1.2 The MIPS Five-Stage Pipeline1.3 RISC and CISC1.4 Great MIPS Chips of the Past and Present1.5 MIPS Compared with CISC Architectures
Chapter 2: MIPS Architecture
2.1 A Flavor of MIPS Assembly Language2.2 Registers2.3 Integer Multiply Unit and Registers2.4 Loading and Storing: Addressing Modes2.5 Data Types in Memory and Registers2.6 Synthesized Instructions in Assembly Language2.7 MIPS I to MIPS64 ISAs: 64-Bit (and Other) Extensions2.8 Basic Address Space2.9 Pipeline Visibility
Chapter 3: Coprocessor 0: MIPS Processor Control
3.1 CPU Control Instructions3.2 Which Registers Are Relevant When?3.3 CPU Control Registers and Their Encoding3.4 CP0 Hazards—A Trap for the Unwary
Chapter 4: How Caches Work on MIPS Processors
4.1 Caches and Cache Management4.2 How Caches Work4.3 Write-Through Caches in Early MIPS CPUs4.4 Write-Back Caches in MIPS CPUs4.5 Other Choices in Cache Design4.6 Managing Caches4.7 L2 and L3 Caches4.8 Cache Configurations for MIPS CPUs4.9 Programming MIPS32/64 Caches4.10 Cache Efficiency4.11 Reorganizing Software to Influence Cache Efficiency4.12 Cache Aliases

Chapter 5: Exceptions, Interrupts, and Initialization
5.1 Precise Exceptions5.2 When Exceptions Happen5.3 Exception Vectors: Where Exception Handling Starts5.4 Exception Handling: Basics5.5 Returning from an Exception5.6 Nesting Exceptions5.7 An Exception Routine5.8 Interrupts5.9 Starting Up5.10 Emulating Instructions
Chapter 6: Low-level Memory Management and the TLB
6.1 The TLB/MMU Hardware and What It Does6.2 TLB/MMU Registers Described6.3 TLB/MMU Control Instructions6.4 Programming the TLB6.5 Hardware-Friendly Page Tables and Refill Mechanism6.6 Everyday Use of the MIPS TLB6.7 Memory Management in a Simpler OS
Chapter 7: Floating-Point Support
7.1 A Basic Description of Floating Point7.2 The IEEE 754 Standard and Its Background7.3 How IEEE Floating-Point Numbers Are Stored7.4 MIPS Implementation of IEEE 7547.5 Floating-Point Registers7.6 Floating-Point Exceptions/Interrupts7.7 Floating-Point Control: The Control/Status Register7.8 Floating-Point Implementation Register7.9 Guide to FP Instructions7.10 Paired-Single Floating-Point Instructions and the MIPS-3D ASE7.11 Instruction Timing Requirements7.12 Instruction Timing for Speed7.13 Initialization and Enabling on Demand7.14 Floating-Point Emulation
Chapter 8: Complete Guide to the MIPS Instruction Set
8.1 A Simple Example8.2 Assembly Instructions and What They Mean8.3 Floating-Point Instructions8.4 Differences in MIPS32/64 Release 18.5 Peculiar Instructions and Their Purposes8.6 Instruction Encodings8.7 Instructions by Functional Group
Chapter 9: Reading MIPS Assembly Language
9.1 A Simple Example9.2 Syntax Overview9.3 General Rules for Instructions9.4 Addressing Modes9.5 Object File and Memory Layout
Chapter 10: Porting Software to the MIPS Architecture
10.1 Low-Level Software for MIPS Applications: A Checklist of Frequently Encountered Problems10.2 Endianness: Words, Bytes, and Bit Order10.3 Trouble with Visible Caches10.4 Memory Access Ordering and Reordering10.5 Writing it in C
Chapter 11: MIPS Software Standards (ABIs)
11.1 Data Representations and Alignment11.2 Argument Passing and Stack Conventions for MIPS ABIs
Chapter 12: Debugging MIPS Designs—Debug and Profiling Features
12.1 The “EJTAG” On-chip Debug Unit12.2 Pre-EJTAG Debug Support—Break Instruction and CPO Watchpoints12.3 PDtrace12.4 Performance Counters
Chapter 13: GNU/Linux from Eight Miles High
13.1 Components13.2 Layering in the Kernel
Chapter 14: How Hardware and Software Work Together
14.1 The Life and Times of an Interrupt14.2 Threads, Critical Regions, and Atomicity14.3 What Happens on a System Call14.4 How Addresses Get Translated in Linux/MIPS Systems
Chapter 15: MIPS Specific Issues in the Linux Kernel
15.1 Explicit Cache Management15.2 CP0 Pipeline Hazards15.3 Multiprocessor Systems and Coherent Caches15.4 Demon Tweaks for a Critical Routine
Chapter 16: Linux Application Code, PIC, and Libraries
16.1 How Link Units Get into a Program16.2 Global Offset Table (GOT) Organization
Appendix A: MIPS Multithreading
A.1 What Is Multithreading?A.2 Why Is MT Useful?A.3 How to Do Multithreading for MIPSA.4 MT in Action
Appendix B: Other Optional Extensions to the MIPS Instruction Set
B.1 MIPS16 and MIPS16e ASEsB.2 The MIPS DSP ASEB.3 The MDMX ASE
MIPS Glossary
References
Books and ArticlesOnline Resources
Index

Content preview from See MIPS Run, 2nd Edition

Chapter 4 How Caches Work on MIPS Processors

A MIPS CPU without a cache isn’t really a RISC. Perhaps that’s not fair; for special purposes you might be able to build a MIPS CPU with a small, tightly coupled memory that can be accessed in a fixed number of pipeline stages (preferably one). But MIPS CPUs have always had cache hardware built tightly into the pipeline.

This chapter will describe the way MIPS caches work and what the software has to do to make caches useful and reliable. From reset, almost everything about the cache state is undefined, so bootstrap software must be careful to initialize the caches correctly before relying on them. You might also benefit from some hints and tips for use when sizing the caches (it would be bad software ...

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See MIPS Run, 2nd Edition

by Dominic Sweetman

Become an O’Reilly member and get unlimited access to this title plus top books and audiobooks from O’Reilly and nearly 200 top publishers, thousands of courses curated by job role, 150+ live events each month,
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