Three-dimensional Integrated Circuit Design

Chapter 8. Timing Optimization for Multiterminal Interconnects

A significant improvement in the performance of two-terminal interplane interconnects in 3-D circuits is demonstrated in the previous chapter. A technique that accurately determines the via location that minimizes the delay of a two-terminal interconnect is described and applied to numerous interconnects. Multiterminal interconnects, however, constitute a significant portion of the interconnects in an integrated circuit. Improving the performance of these nets in 3-D circuits is a challenging task as the sinks of these interconnects can be located on different physical planes. In addition to decreasing the delay, a timing optimization technique should not significantly affect the ...