Three-dimensional Integrated Circuit Design

Appendix C. Proof of the Two-Terminal Via Placement Heuristic

A formal proof of the two-terminal heuristic for placing interplane vias is described in this appendix. Consider the following expression that describes the critical point (i.e., the derivative of the delay is set equal to zero) for placing a via v^j, as illustrated in Fig. C-1,(C-1)

Figure Figure C-1. Interplane interconnect consisting of m segments connecting two circuits located n planes apart.

From this expression, the critical point x^j is a monotonic function of the upstream resistance ...