VHDL 101

Index

A

Accidental latch interference

68, 116

Addition function

181–82

Advanced Silicon Modular Block (ASMBL)

4–5

Aggregates

40, 42–43

Aliases

149–50

“all” keyword

147

Analog-to-digital converters

56, 84

“and” function/gate

48–49, 92–94, 99, 186

Architecture

28–29, 136

behavioral

72, 80, 81, 118

FPGA

4–10, 12

UART design

75–78

VHDL module structure

19–21

“arguments”

165

Arrays:

aggregates

40–41

composite data types

38–40

data types

34–37

NUMERIC_STD

187–89

signed/unsigned

187–89

slices

40–41

Ashenden, Peter

2

ASMBL

seeAdvanced Silicon Modular Block

Assignment:

concurrent statements

33, 59–77

conditional

64–69, 113–15, 136

positional

72, 174

signals

32–33

unconditional

63–64, 113

Asynchronous processes

92, 110–13, 114, 117, 132

Attributes

176–80

B

Baud rates

77–81, 117, 123, 123–26, 128–29, 132

Behavior of ...