book

Customizable Embedded Processors Design Technologies and Applications

by Rainer Leupers, Paolo Ienne

July 2006

Intermediate to advanced

528 pages

13h 28m

English

Morgan Kaufmann

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Copyright
Dedication
In Praise of Customizable Embedded Processors
The Morgan Kaufmann Series in Systems on Silicon
List of Contributors
About the Editors
I. Opportunities and Challenges
1. From Prêt-à-Porter to Tailor-Made
1.1. The Call for Flexibility1.2. Cool Chips for Shallow Pockets1.3. A Million Processors for the Price of One?1.4. Processors Coming of Age1.5. This Book1.6. Travel Broadens the Mind
2. Opportunities for Application-Specific Processors: The Case of Wireless Communications
2.1. Future Mobile Communication Systems2.2. Heterogeneous MPSoC for Digital Receivers2.2.1. The Fundamental Tradeoff between Energy Efficiency and Flexibility2.2.2. How to Exploit the Huge Design Space?2.2.3. Canonical Receiver Structure2.2.4. Analyzing and Classifying the Functions of a Digital ReceiverStep 1: Identify structural and temporal properties of the taskExample: DVB-S ReceiverStep 2: From function to algorithmExample: Cordic AlgorithmStep 3: Define algorithmic descriptorsStep 4: Classification of the algorithmExample: Baseband Processing for a 384-Kbps UMTS ReceiverExample: UWB ReceiverExample 3: Multimedia Signal Processing2.2.5. Exploiting Parallelism2.3. ASIP Design2.3.1. Processor Design Flow2.3.2. Architecture Description Language Based Design2.3.3. Too Much Automation Is Bad2.3.4. Processor Design: The LISATek Approach2.3.5. Design Competence Rules the WorldExample: FFT Implementation2.3.6. Application-Specific or Domain-Specific Processors?
3. Customizing Processors: Lofty Ambitions, Stark Realities
3.1. The “CFP” project at HP Labs3.2. Searching for the Best Architecture Is Not a Machine-Only Endeavor3.3. Designing a CPU Core Still Takes a Very Long Time3.4. Don’t Underestimate Competitive Technologies3.5. Software Developers Don’t Always Help You3.6. The Embedded World Is Not Immune to Legacy Problems3.7. Customization Can Be Trouble3.8. Conclusions
II. Aspects of Processor Customization

4. Architecture Description Languages
4.1. ADLs and other languages4.2. Survey of Contemporary ADLs4.2.1. Content-Oriented Classification of ADLsStructural ADLsMIMOLABehavioral ADLsnMLISDLMixed ADLsHMDESExpressionLISA4.2.2. Objective-Based Classification of ADLsCompilation-Oriented ADLsSimulation-Oriented ADLsSynthesis-Oriented ADLsValidation-Oriented ADLs4.3. Conclusions
5. C Compiler Retargeting
5.1. Compiler Construction Background5.1.1. Source Language Frontend5.1.2. Intermediate Representation and Optimization5.1.3. Machine Code GenerationCode SelectionRegister AllocationInstruction SchedulingOther Backend Optimizations5.2. Approaches to Retargetable Compilation5.2.1. MIMOLA5.2.2. GNU C Compiler5.2.3. Little C Compiler5.2.4. CoSy5.3. Processor Architecture Exploration5.3.1. Methodology and Tools for ASIP Design5.3.2. ADL-Based Approach5.4. C Compiler Retargeting in the LISATek Platform5.4.1. Concept5.4.2. Register Allocator and Scheduler5.4.3. Code Selector5.4.4. Results5.5. Summary and OutlookAcknowledgments
6. Automated Processor Configuration and Instruction Extension
6.1. Automation Is Essential for ASIP Proliferation6.2. The Tensilica Xtensa LX Configurable Processor6.3. Generating ASIPs Using Xtensa6.4. Automatic Generation of ASIP Specifications6.5. Coding an Application for Automatic ASIP Generation6.6. XPRES Benchmarking Results6.7. Techniques for ASIP Generation6.7.1. Reference Examples for Evaluating XPRES6.7.2. VLIW-FLIX: Exploiting Instruction Parallelism6.7.3. SIMD (Vectorization): Exploiting Data Parallelism6.7.4. Operator Fusion: Exploiting Pipeline Parallelism6.7.5. Combining Techniques6.8. Exploring the Design Space6.9. Evaluating Xpres Estimation Methods6.9.1. Application Performance Estimation6.9.2. ASIP Area Estimation6.9.3. Characterization Benchmarks6.9.4. Performance and Area Estimation6.10. Conclusions and Future of the Technology
7. Automatic Instruction-Set Extensions
7.1. Beyond Traditional Compilers7.1.1. Structure of the Chapter7.2. Building Block for Instruction Set Extension7.2.1. Motivation7.2.2. Problem Statement: Identification and Selection7.2.3. Identification Algorithm7.2.4. Results7.3. Heuristics7.3.1. Motivation7.3.2. Types of Heuristic Algorithms7.3.3. A Partitioning-Based Heuristic Algorithm7.3.4. A Clustering Heuristic Algorithm7.4. State-Holding Instruction-Set Extensions7.4.1. Motivation7.4.2. Local-Memory Identification Algorithm7.4.3. Results7.5. Exploiting Pipelining to Relax I/O Constraints7.5.1. Motivation7.5.2. Reuse of the Basic Identification Algorithm7.5.3. Problem Statement: Pipelining7.5.4. I/O Constrained Scheduling Algorithm7.5.5. Results7.6. Conclusions and Further Challenges
8. Challenges to Automatic Customization
8.1. The ARCompact™ Instruction Set Architecture8.1.1. Mechanisms for Architecture Extension8.1.2. ARCompact Implementations8.2. Microarchitecture Challenges8.3. Case Study—Entropy Decoding8.3.1. Customizing VLD Extensions8.4. Limitations of Automated Extension8.5. The Benefits of Architecture Extension8.5.1. Customization Enables CoDesign8.5.2. Customization Offers Performance Headroom8.5.3. Customization Enables Platform IP8.5.4. Customization Enables Differentiation8.6. Conclusions
9. Coprocessor Generation from Executable Code
9.1. Introduction9.2. User Level Flow9.3. Integration with Embedded Software9.4. Coprocessor Architecture9.5. ILP Extraction Challenges9.6. Internal Tool Flow9.7. Code Mapping Approach9.8. Synthesizing Coprocessor Architectures9.9. A Real-World Example9.10. Summary
10. Datapath Synthesis
10.1. Introduction10.2. Custom Instruction Selection10.3. Theoretical Preliminaries10.3.1. The Minimum Area-Cost Acyclic Common Supergraph Problem10.3.2. Subsequence and Substring Matching Techniques10.4. Minimum Area-Cost Acyclic Common Supergraph Heuristic10.4.1. Path-Based Resource Sharing10.4.2. Example10.4.3. Pseudocode10.5. Multiplexer Insertion10.5.1. Unary and Binary Noncommutative Operators10.5.2. Binary Commutative Operators10.6. Datapath Synthesis10.6.1. Pipelined Datapath Synthesis10.6.2. High-Level Synthesis10.7. Experimental Results10.8. Conclusion
11. Instruction Matching and Modeling
11.1. Matching Instructions11.1.1. Introduction to Binary Decision Diagrams11.1.2. The Translator11.1.3. Filtering Algorithm11.1.4. Combinational Equivalence Checking Model11.1.5. Results11.2. Modeling11.2.1. Overview11.2.2. Customization Parameters11.2.3. Characterization for Various ConstraintsArea Overhead CharacterizationLatency CharacterizationPower Consumption Characterization11.2.4. Equations for Estimating Area, Latency, and Power Consumption11.2.5. Evaluation Results11.3. ConclusionsAppendix: Estimating Area, Latency, and Power ConsumptionA.1 Area Overhead EstimationA.2 Latency EstimationA.3 Power Consumption Estimation
12. Processor Verification
12.1. Motivation12.2. Overview of Verification Approaches12.2.1. Simulation12.2.2. Semiformal Techniques12.2.3. Proof Techniques12.2.4. Coverage12.3. Formal Verification of a RISC CPU12.3.1. Verification Approach12.3.2. Specification12.3.3. SystemC Model12.3.4. Formal VerificationHardwareInterfaceProgram12.4. Verification Challenges in Customizable and Configurable Embedded Processors12.5. Verification of Processor Peripherals12.5.1. Coverage-Driven Verification Based on Constrained-Random Stimulation12.5.2. Assertion-Based Verification of Corner Cases12.5.3. Case Study: Verification of an On-Chip Bus Bridge12.6. Conclusions
13. Sub-RISC Processors
13.1. Concurrent Architectures, Concurrent Applications13.2. Motivating Sub-RISC PEs13.2.1. RISC PEsDatatype-Level ConcurrencyData-Level ConcurrencyProcess-Level Concurrency13.2.2. Customizable Datapaths13.2.3. Synthesis Approaches13.2.4. Architecture Description LanguagesGenerating the Architecture from the Instruction SetExtracting the Instruction Set from the ArchitectureTIPI Processing Elements13.3. Designing TIPI Processing Elements13.3.1. Building Datapath Models13.3.2. Operation Extraction13.3.3. Single PE Simulator Generation13.3.4. TIPI Multiprocessors13.3.5. Multiprocessor Simulation and RTL Code Generation13.4. Deploying Applications with Cairn13.4.1. The Cairn Application Abstraction13.4.2. Model Transforms13.4.3. Mapping Models13.4.4. Code Generation13.5. IPv4 Forwarding Design Example13.5.1. Designing a PE for ClickApplication KnowledgeArchitectural KnowledgePrior Experience13.5.2. ClickPE Architecture13.5.3. ClickPE Control Logic13.5.4. LuleaPE Architecture13.6. Performance Results13.6.1. ClickPE Performance13.6.2. LuleaPE Performance13.6.3. Performance Comparison13.6.4. Potentials for Improvement13.7. ConclusionAcknowledgments
III. Case Studies
14. Application Specific Instruction Set Processor for UMTS-FDD Cell Search
14.1. ASIP on Wireless Modem Design14.1.1. The Role of ASIP14.1.2. ASIP Challenges for a System House14.1.3. Potential ASIP Use Cases in Wireless Receivers14.2. Functionality of Cell Search ASIP14.2.1. Cell Search–Related Channels and Codes14.2.2. Cell Search Functions14.2.3. Requirements for the ASIP14.3. Cell Search ASIP Design and Verification14.3.1. Microarchitecture14.3.2. Special Function Units14.3.3. Instruction Set14.3.4. HDL Generation14.3.5. Verification14.4. Results14.4.1. Performance14.4.2. Synthesis Results14.5. Summary and Conclusions
15. Hardware/Software Tradeoffs for Advanced 3G Channel Decoding
15.1. Channel Decoding for 3G Systems and Beyond15.1.1. Turbo-Codes15.2. Design Space15.3. Programmable Solutions15.3.1. VLIW Architectures15.3.2. Customizable Processors15.4. Multiprocessor Architectures15.5. Conclusion
16. Application Code Profiling and ISA Synthesis on MIPS32
16.1. Profiling of Application Source Code16.1.1. Assembly and Source Level Profiling16.1.2. Microprofiling Approach16.1.3. Memory Access Microprofiling16.1.4. Experimental Results16.2. Semiautomatic ISA Extension Synthesis16.2.1. Sample Platform: MIPS CorExtend16.2.2. CoWare CorXpert Tool16.2.3. ISA Extension Synthesis Problem16.2.4. Synthesis Core Algorithm16.2.5. ISA Synthesis–Based Design Flow16.2.6. Speedup Estimation16.2.7. Exploring the Design Space16.2.8. SW Tools Retargeting and Architecture Implementation16.2.9. Case Study: Instruction Set Customization for Blowfish EncryptionAutomatic CI Identification for BlowfishUse of Scratch-Pad Memories16.3. Summary and OutlookAcknowledgements
17. Designing Soft Processors for FPGAs
17.1. Overview17.1.1. FPGA Architecture Overview17.1.2. Soft Processors in FPGAs17.1.3. Overview of Processor Acceleration17.2. MicroBlaze Soft Processor Architecture17.2.1. Short Description of MicroBlaze17.2.2. Highlights of Architectural Features17.3. Discussion of Architectural Design Tradeoffs in MicroBlaze17.3.1. Architectural Building-Blocks and Their FPGA ImplementationFPGA Logic and Memory Structures17.3.2. Examples of Architectural Decisions in MicroBlazeInstruction Set DesignDatapath DesignImplementation-Specific DetailsPerformance of Soft ProcessorsCustom Instructions and Function Acceleration17.3.3. Tool Support17.4. ConclusionsAcknowledgements
Chapter References
Chapter 1Chapter 2Chapter 3Chapter 4Chapter 5Chapter 6Chapter 7Chapter 8Chapter 9Chapter 10Chapter 11Chapter 12Chapter 13Chapter 14Chapter 15Chapter 16Chapter 17
Bibliography

Overview

Customizable processors have been described as the next natural step in the evolution of the microprocessor business: a step in the life of a new technology where top performance alone is no longer sufficient to guarantee market success. Other factors become fundamental, such as time to market, convenience, energy efficiency, and ease of customization. This book is the first to explore comprehensively one of the most fundamental trends which emerged in the last decade: to treat processors not as rigid, fixed entities, which designers include "as is" in their products; but rather, to build sound methodologies to tailor-fit processors to the specific needs of such products. This book addresses the goal of maintaining a very large family of processors, with a wide range of features, at a cost comparable to that of maintaining a single processor.

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