All-Digital Frequency Synthesizer in Deep-Submicron CMOS

INDEX

Acquisition mode, 40–41, 44–45, 147

Acquisition time, 16

Additive white Gaussian noise (AWGN), 193

ADPLL (all-digital PLL), 23, 76

clock names, 81

clock retiming, 103

difference mode, 85

direct modulation, 159

fractional error correction, 82

fractional phase, 91

frequency control word (FCW), 78, 116, 149, 156

frequency response, 115

type I, 116

type II, 130

higher-order, 133, 135

integer-domain operation, 86

linear model, 119

loop

bandwidth, 113, 117, 128

delay, 116

filter, 115

proportional-integral control, 127

loop gain, 109

attenuation, 110

damping, 110

gear shifting, 142, 153

programmable, 113

proportionality factor, 111

metastability, 79, 100, 103

modeling, 189

arithmetic, 84

noise, 119

DCO noise, 119

TDC noise, 120

nonlinear differential term, 139

performance, 221

switching transient, 224

phase

accumulators, 86, 89

comparison, 79

detection, 83

estimate, 81

reference, 78, 82, 86, 113

resolution, 113

variable, 82, 89

phase error, 82, 111

excess, 111, 149–151

instantaneous variation, 139

excess, 111

phase noise spectrum, 121, 126, 222–223

phase-domain

architecture, 112

structure, 24

operation, 77, 79

power spectral density, 222, 229

proportional-integral control, 127

quantization error, 80

reference clock (FREF), 1, 76–77

retiming, 79, 100

reference phase, 77–78

retimed reference (CKR), 79, 103, 113

s-domain model, 115, 118

scaling factor, 110

stability analysis, 137

TDC (time-to-digital converter), 91

transfer function

closed-loop, 116, 131

open-loop, 116, 130–131

transmitter ...