Analog Interfacing to Embedded Microprocessor Systems, 2nd Edition

If the converter shown in Figure 2.7 were a 0–5 V converter converting a 3.1 V

input, then the conversion would look like this:

Upper flash converter output ¼ 9

DAC output ¼ 2:8125 Vð9  16  19:53 mvÞ

Subtracter output ¼ 3:1 V  2:8125 V ¼ 0:2875 V

Lower flash converter output ¼ E ðhexÞ

Final result ¼ 9E (hex), 158 (decimal)

Half-flash converters can also use three stages instead of two; a 12-bit converter

might have three stages of 4 bits each. The result of the MS 4 bits would be

subtracted from the input voltage and applied to the middle 4-bit state. The result

of the middle stage would be subtracted from its input and applied to the least

significant ...