Architectures for Computer Vision: From Algorithm to Chip with Verilog

Architectures for Computer Vision: From Algorithm to Chip with Verilog

by Hong Jeong
Released October 2014
Publisher(s): Wiley
ISBN: 9781118659182

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Book description

This book provides comprehensive coverage of 3D vision systems, from vision models and state-of-the-art algorithms to their hardware architectures for implementation on DSPs, FPGA and ASIC chips, and GPUs. It aims to fill the gaps between computer vision algorithms and real-time digital circuit implementations, especially with Verilog HDL design. The organization of this book is vision and hardware module directed, based on Verilog vision modules, 3D vision modules, parallel vision architectures, and Verilog designs for the stereo matching system with various parallel architectures. It provides Verilog vision simulators, tailored to the design and testing of general vision chips. It bridges the differences between C/C++ and HDL to encompass both software realization and chip implementation; includes numerous examples that realize vision algorithms and general vision processing in HDL. It is unique in providing an organized and complete overview of how a real-time 3D vision system-on-chip can be designed. It focuses on the digital VLSI aspects and implementation of digital signal processing tasks on hardware platforms such as ASICs and FPGAs for 3D vision systems, which have not been comprehensively covered in one single book. It provides a timely view of the pervasive use of vision systems and the challenges of fusing information from different vision modules. The accompanying website includes software and HDL code packages to enhance further learning and develop advanced systems. A solution set and lecture slides are provided on the book's companion website. The book is aimed at graduate students and researchers in computer vision and embedded systems, as well as chip and FPGA designers. Senior undergraduate students specializing in VLSI design or computer vision will also find the book to be helpful in understanding advanced applications.

Table of contents

  1. About the Author
  2. Preface
  3. Part One: Verilog HDL
    1. Chapter 1: Introduction
      1. 1.1 Computer Architectures for Vision
      2. 1.2 Algorithms for Computer Vision
      3. 1.3 Computing Devices for Vision
      4. 1.4 Design Flow for Vision Architectures
      5. Problems
      6. References
    2. Chapter 2: Verilog HDL, Communication, and Control
      1. 2.1 The Verilog System
      2. 2.2 Hello, World!
      3. 2.3 Modules and Ports
      4. 2.4 UUT and TB
      5. 2.5 Data Types and Operations
      6. 2.6 Assignments
      7. 2.7 Structural-Behavioral Design Elements
      8. 2.8 Tasks and Functions
      9. 2.9 Syntax Summary
      10. 2.10 Simulation-Synthesis
      11. 2.11 Verilog System Tasks and Functions
      12. 2.12 Converting Vision Algorithms into Verilog HDL Codes
      13. 2.13 Design Method for Vision Architecture
      14. 2.14 Communication by Name Reference
      15. 2.15 Synchronous Port Communication
      16. 2.16 Asynchronous Port Communication
      17. 2.17 Packing and Unpacking
      18. 2.18 Module Control
      19. 2.19 Procedural Block Control
      20. Problems
      21. References
    3. Chapter 3: Processor, Memory, and Array
      1. 3.1 Image Processing System
      2. 3.2 Taxonomy of Algorithms and Architectures
      3. 3.3 Neighborhood Processor
      4. 3.4 BP Processor
      5. 3.5 DP Processor
      6. 3.6 Forward and Backward Processors
      7. 3.7 Frame Buffer and Image Memory
      8. 3.8 Multidimensional Array
      9. 3.9 Queue
      10. 3.10 Stack
      11. 3.11 Linear Systolic Array
      12. Problems
      13. References
    4. Chapter 4: Verilog Vision Simulator
      1. 4.1 Vision Simulator
      2. 4.2 Image Format Conversion
      3. 4.3 Line-based Vision Simulator Principle
      4. 4.4 LVSIM Top Module
      5. 4.5 LVSIM IO System
      6. 4.6 LVSIM RAM and Processor
      7. 4.7 Frame-based Vision Simulator Principle
      8. 4.8 FVSIM Top Module
      9. 4.9 FVSIM IO System
      10. 4.10 FVSIM RAM and Processor
      11. 4.11 OpenCV Interface
      12. Problems
      13. References
  4. Part Two: Vision Principles
    1. Chapter 5: Energy Function
      1. 5.1 Discrete Labeling Problem
      2. 5.2 MRF Model
      3. 5.3 Energy Function
      4. 5.4 Energy Function Models
      5. 5.5 Free Energy
      6. 5.6 Inference Schemes
      7. 5.7 Learning Methods
      8. 5.8 Structure of the Energy Function
      9. 5.9 Basic Energy Functions
      10. Problems
      11. References
    2. Chapter 6: Stereo Vision
      1. 6.1 Camera Systems
      2. 6.2 Camera Matrices
      3. 6.3 Camera Calibration
      4. 6.4 Correspondence Geometry
      5. 6.5 Camera Geometry
      6. 6.6 Scene Geometry
      7. 6.7 Rectification
      8. 6.8 Appearance Models
      9. 6.9 Fundamental Constraints
      10. 6.10 Segment Constraints
      11. 6.11 Constraints in Discrete Space
      12. 6.12 Constraints in Frequency Space
      13. 6.13 Basic Energy Functions
      14. Problems
      15. References
    3. Chapter 7: Motion and Vision Modules
      1. 7.1 3D Motion
      2. 7.2 Direct Motion Estimation
      3. 7.3 Structure from Optical Flow
      4. 7.4 Factorization Method
      5. 7.5 Constraints on the Data Term
      6. 7.6 Continuity Equation
      7. 7.7 The Prior Term
      8. 7.8 Energy Minimization
      9. 7.9 Binocular Motion
      10. 7.10 Segmentation Prior
      11. 7.11 Blur Diameter
      12. 7.12 Blur Diameter and Disparity
      13. 7.13 Surface Normal and Disparity
      14. 7.14 Surface Normal and Blur Diameter
      15. 7.15 Links between Vision Modules
      16. Problems
      17. References
  5. Part Three: Vision Architectures
    1. Chapter 8: Relaxation for Energy Minimization
      1. 8.1 Euler–Lagrange Equation of the Energy Function
      2. 8.2 Discrete Diffusion and Biharminic Operators
      3. 8.3 SOR Equation
      4. 8.4 Relaxation Equation
      5. 8.5 Relaxation Graph
      6. 8.6 Relaxation Machine
      7. 8.7 Affine Graph
      8. 8.8 Fast Relaxation Machine
      9. 8.9 State Memory of Fast Relaxation Machine
      10. 8.10 Comparison of Relaxation Machines
      11. Problems
      12. References
    2. Chapter 9: Dynamic Programming for Energy Minimization
      1. 9.1 DP for Energy Minimization
      2. 9.2 N-best Parallel DP
      3. 9.3 N-best Serial DP
      4. 9.4 Extended DP
      5. 9.5 Hidden Markov Model
      6. 9.6 Inside-Outside Algorithm
      7. Problems
      8. References
    3. Chapter 10: Belief Propagation and Graph Cuts for Energy Minimization
      1. 10.1 Belief in MRF Factor System
      2. 10.2 Belief in Pairwise MRF System
      3. 10.3 BP in Discrete Space
      4. 10.4 BP in Vector Space
      5. 10.5 Flow Network for Energy Function
      6. 10.6 Swap Move Algorithm
      7. 10.7 Expansion Move Algorithm
      8. Problems
      9. References
  6. Part Four: Verilog Design
    1. Chapter 11: Relaxation for Stereo Matching
      1. 11.1 Euler–Lagrange Equation
      2. 11.2 Discretization and Iteration
      3. 11.3 Relaxation Algorithm for Stereo Matching
      4. 11.4 Relaxation Machine
      5. 11.5 Overall System
      6. 11.6 IO Circuit
      7. 11.7 Updation Circuit
      8. 11.8 Circuit for the Data Term
      9. 11.9 Circuit for the Differential
      10. 11.10 Circuit for the Neighborhood
      11. 11.11 Functions for Saturation Arithmetic
      12. 11.12 Functions for Minimum Argument
      13. 11.13 Simulation
      14. Problems
      15. References
    2. Chapter 12: Dynamic Programming for Stereo Matching
      1. 12.1 Search Space
      2. 12.2 Line Processing
      3. 12.3 Computational Space
      4. 12.4 Energy Equations
      5. 12.5 DP Algorithm
      6. 12.6 Architecture
      7. 12.7 Overall Scheme
      8. 12.8 FIFO Buffer
      9. 12.9 Reading and Writing
      10. 12.10 Initialization
      11. 12.11 Forward Pass
      12. 12.12 Backward Pass
      13. 12.13 Combinational Circuits
      14. 12.14 Simulation
      15. Problems
      16. References
    3. Chapter 13: Systolic Array for Stereo Matching
      1. 13.1 Search Space
      2. 13.2 Systolic Transformation
      3. 13.3 Fundamental Systolic Arrays
      4. 13.4 Search Spaces of the Fundamental Systolic Arrays
      5. 13.5 Systolic Algorithm
      6. 13.6 Common Platform of the Circuits
      7. 13.7 Forward Backward and Right Left Algorithm
      8. 13.8 FBR and FBL Overall Scheme
      9. 13.9 FBR and FBL FIFO Buffer
      10. 13.10 FBR and FBL Reading and Writing
      11. 13.11 FBR and FBL Preprocessing
      12. 13.12 FBR and FBL Initialization
      13. 13.13 FBR and FBL Forward Pass
      14. 13.14 FBR and FBL Backward Pass
      15. 13.15 FBR and FBL Simulation
      16. 13.16 Backward Backward and Right Left Algorithm
      17. 13.17 BBR and BBL Overall Scheme
      18. 13.18 BBR and BBL Initialization
      19. 13.19 BBR and BBL Forward Pass
      20. 13.20 BBR and BBL Backward Pass
      21. 13.21 BBR and BBL Simulation
      22. Problems
      23. References
    4. Chapter 14: Belief Propagation for Stereo Matching
      1. 14.1 Message Representation
      2. 14.2 Window Processing
      3. 14.3 BP Machine
      4. 14.4 Overall System
      5. 14.5 IO Circuit
      6. 14.6 Sampling Circuit
      7. 14.7 Circuit for the Data Term
      8. 14.8 Circuit for the Input Belief Message Matrix
      9. 14.9 Circuit for the Output Belief Message Matrix
      10. 14.10 Circuit for the Updation of Message Matrix
      11. 14.11 Circuit for the Disparity
      12. 14.12 Saturation Arithmetic
      13. 14.13 Smoothness
      14. 14.14 Minimum Argument
      15. 14.15 Simulation
      16. Problems
      17. References
  7. Index
  8. End User License Agreement

Product information

  • Title: Architectures for Computer Vision: From Algorithm to Chip with Verilog
  • Author(s): Hong Jeong
  • Release date: October 2014
  • Publisher(s): Wiley
  • ISBN: 9781118659182