2.1 The Verilog System2.2 Hello, World!2.3 Modules and Ports2.4 UUT and TB2.5 Data Types and Operations2.6 Assignments2.7 Structural-Behavioral Design Elements2.8 Tasks and Functions2.9 Syntax Summary2.10 Simulation-Synthesis2.11 Verilog System Tasks and Functions2.12 Converting Vision Algorithms into Verilog HDL Codes2.13 Design Method for Vision Architecture2.14 Communication by Name Reference2.15 Synchronous Port Communication2.16 Asynchronous Port Communication2.17 Packing and Unpacking2.18 Module Control2.19 Procedural Block ControlProblemsReferences