CMOS Analog Integrated Circuits

13

Circuits for Clock Signal Generation and Synchronization

13.1  Generation of clock signals with nonoverlapping phases

13.2  Phase-locked loop

13.2.1  PLL linear model

13.2.2  Charge-pump PLL

13.3  Charge-pump PLL building blocks

13.3.1  Phase and frequency detector

13.3.2  Phase detector

13.3.2.1  Linear phase detector

13.3.2.2  Binary phase detector

13.3.2.3  Half-rate phase detector

13.3.3  Charge-pump circuit

13.3.4  Loop filter

13.3.5  Voltage-controlled oscillator

13.4  Applications

13.4.1  Frequency synthesizer

13.4.2  Clock and data recovery

13.5  Delay-locked loop

13.6  PLL with a built-in self-test structure

13.7  PLL specifications

13.8  Summary

13.9  Circuit design assessment

A circuit for the clock signal generation or recovery ...