book

CMOS Analog Integrated Circuits

by Tertulien Ndjountche

December 2017

Intermediate to advanced

926 pages

22h 26m

English

CRC Press

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Content overviewFeedbackAcknowledgments
1.1 Integrated circuit design flow1.2 Design technique issues1.3 Integrated system perspectives1.4 Built-in self-test structures1.5 Concluding remarks1.6 To probe further
2.1 Transistor structure2.1.1 I/V characteristics of MOS transistors2.1.2 Drain current in the strong inversion approximation2.1.3 Drain current in the subthreshold region2.1.4 MOS transistor capacitances2.1.5 Scaling effects on MOS transistors2.2 Transistor SPICE models2.2.1 Electrical characteristics2.2.2 Temperature effects2.2.3 Noise models2.3 Summary2.4 Circuit design assessmentBibliography

3.1 MOS Transistors3.2 Passive components3.2.1 Capacitors3.2.2 Resistors3.2.3 Inductors3.3 Integrated-circuit (IC) interconnects3.4 Physical design considerations3.5 IC packaging3.6 Summary3.7 Circuit design assessmentBibliography
4.1 Current mirrors4.1.1 Simple current mirror4.1.2 Cascode current mirror4.1.3 Low-voltage active current mirror4.2 Current and voltage references4.2.1 Supply-voltage independent current reference4.2.2 Bandgap references4.2.2.1 Low-voltage bandgap voltage reference4.2.2.2 Curvature-compensated bandgap voltage reference4.2.3 Floating-gate voltage reference4.3 Summary4.4 Circuit design assessmentBibliography
5.1 Differential amplifier5.1.1 Dynamic range5.1.2 Source-coupled differential transistor pair5.1.3 Current mirror5.1.4 Slew-rate limitation5.1.5 Small-signal characteristics5.1.6 Offset voltage5.1.7 Noise in a differential transistor pair5.1.8 Operational amplifier5.2 Linearization techniques for transconductors5.3 Single-stage amplifier
5.5 Fully differential amplifier architectures5.5.1 Fully differential folded-cascode amplifier5.5.1.1 Basic structure5.5.1.2 Gain-enhanced structure5.5.2 Telescopic amplifier5.5.3 Common-mode feedback circuits5.5.3.1 Continuous-time common-mode feedback circuit5.5.3.2 Switched-capacitor common-mode feedback circuit5.5.4 Pseudo fully differential amplifier5.6 Multi-stage amplifier structures5.6.1 Output stage5.6.2 Two-stage amplifier
5.6.4 Three-stage amplifier5.7 Rail-to-rail amplifiers5.7.1 Amplifier with a class AB input stage5.7.2 Two-stage amplifier with class AB output stage5.7.3 Amplifier with rail-to-rail input and output stages5.8 Amplifier characterization5.8.1 Finite gain and bandwidth5.8.2 Phase margin5.8.3 Input and output impedances5.8.4 Power supply rejection5.8.5 Slew rate5.8.6 Low-frequency noise and dc offset voltage5.8.6.1 Auto-zero compensation scheme5.8.6.2 Chopper technique5.9 Summary5.10 Circuit design assessmentBibliography
6.1 Comparators6.1.1 Amplifier-based comparator6.1.2 Comparator using charge balancing techniques6.1.3 Latched comparators6.1.3.1 Static comparator6.1.3.2 Dynamic comparator6.2 Multipliers6.2.1 Multiplier cores6.2.1.1 Multiplier core based on externally controlled transconductances6.2.1.2 Multiplier core based on the quarter-square technique6.2.1.3 Design issues6.2.2 Design examples6.3 Summary6.4 Circuit design assessmentBibliography
7.1 Wireless communication system7.1.1 Receiver and transmitter architectures7.1.2 Frequency translation and quadrature multiplexing7.1.3 Architecture of a harmonic-rejection transceiver7.1.4 Amplifiers7.1.4.1 Power amplifier7.1.4.2 Low-noise amplifier7.1.5 Mixer7.1.6 Voltage-controlled oscillator7.1.7 Automatic gain control7.2 Continuous-time filters7.2.1 RC circuits
7.2.3 gm-C circuits7.2.4 gm-C operational amplifier (OA) circuits7.2.5 Summer circuits7.2.6 Gyrator7.3 Filter characterization7.4 Filter design methods7.4.1 First-order filter design7.4.2 Biquadratic filter design methods7.4.2.1 Signal-flow graph-based design7.4.2.2 Gyrator-based design7.4.3 Ladder filter design methods7.4.3.1 LC ladder network-based design7.4.3.2 Signal-flow graph-based design7.5 Design considerations for continuous-time filters7.5.1 Automatic on-chip tuning of continuous-time filters7.5.2 Nonideal integrator7.6 Frequency-control systems7.6.1 Phase-locked-loop-based technique7.6.1.1 Operation principle7.6.1.2 Architecture of the master: VCO or VCF7.6.1.3 Phase detector7.6.1.4 Implementation issues7.6.2 Charge comparison-based technique7.7 Quality-factor and bandwidth control systems7.7.1 Magnitude-locked-loop-based technique7.7.2 Envelope detection-based technique
7.9 Other tuning strategies7.9.1 Tuning scheme using an external resistor7.9.2 Self-tuned filter7.9.3 Tuning scheme based on adaptive filter technique7.10 Summary7.11 Circuit design assessmentBibliography
8.1 Anti-aliasing filter8.2 Capacitors8.3 Switches8.3.1 Switch description8.3.2 Switch error sources8.3.3 Switch compensation techniques8.4 Programmable capacitor arrays8.5 Operational amplifiers
8.7 Switched-capacitor (SC) circuit principle8.8 SC filter design8.8.1 First-order filter8.8.2 Biquad filter8.8.3 Ladder filter8.9 SC ladder filter based on the LDI transform8.10 SC ladder filter based on the bilinear transform8.10.1 RLC filter prototype-based design8.10.2 Transfer function-based design of allpass filters
8.11.1 Amplifier dc gain8.11.2 Amplifier finite bandwidth8.11.2.1 Inverting integrator8.11.2.2 Noninverting integrator8.12 Settling time in the integrator8.13 Amplifier dc offset voltage limitations8.14 Computer-aided analysis of SC circuits8.15 T/H and S/H circuits based on SC circuit principle8.16 Circuit structures with low sensitivity to nonidealities8.16.1 Integrators8.16.2 Gain stages8.17 Low-voltage SC circuits8.18 Summary8.19 Circuit design assessmentBibliography
9.1 Binary codes9.1.1 Unipolar codes9.1.2 Bipolar codes9.1.3 Remarks9.2 Data converter characterization9.2.1 Quantization errors9.2.2 Errors related to circuit components9.2.3 Static errors9.2.4 Dynamic errors9.3 SummaryBibliography
10.1 Digital-to-analog converter (DAC) architectures10.1.1 Binary-weighted structure10.1.2 Thermometer-coded structure10.1.3 Segmented architecture10.2 Voltage-scaling DACs10.2.1 Basic resistor-string DAC10.2.2 Intermeshed resistor-string DAC10.2.3 Two-stage resistor-string DAC10.3 Current-scaling DACs10.3.1 Binary-weighted resistor DAC10.3.2 R-2R ladder DAC10.3.3 Switched-current DAC10.4 Charge-scaling DAC10.5 Hybrid DAC10.6 Configuring a unipolar DAC for the bipolar conversion10.7 Algorithmic DAC10.8 Summary10.9 Circuit design assessmentBibliography
11.1 Analog-to-digital converter (ADC) architectures11.1.1 Successive approximation register ADC11.1.2 Integrating ADC11.1.3 Flash ADC11.1.4 Averaging ADC11.1.5 Folding and interpolating ADC11.1.6 Sub-ranging ADC11.1.7 Pipelined ADC
11.1.9 Time-interleaved ADC11.2 Summary11.3 Circuit design assessmentBibliography
12.1 Delta-sigma analog-to-digital converter12.1.1 Time domain behavior12.1.2 Linear model of a discrete-time modulator12.1.3 Modulator dynamic range12.1.4 Continuous-time modulator12.1.5 Lowpass delta-sigma modulator12.1.5.1 Single-stage modulator with a 1-bit quantizer12.1.5.2 Dithering12.1.5.3 Design examples12.1.5.4 Modulator architectures with a multi-bit quantizer12.1.5.5 Cascaded modulator12.1.5.6 Effect of the multi-bit DAC nonlinearity12.1.5.7 Quantization noise shaping and inter-stage coefficient scaling12.1.6 Bandpass delta-sigma modulator12.1.6.1 Single-loop bandpass delta-sigma modulator12.1.6.2 Cascaded bandpass delta-sigma modulator12.1.6.3 Design examples
12.2 Delta-sigma digital-to-analog converter12.2.1 Interpolation filter12.2.2 Digital modulator12.3 Nyquist DAC design issues12.3.1 Data-weighted averaging technique12.3.2 Element selection logic based on a tree structure and butterfly shuffler
12.4 Data converter testing and characterization12.4.1 Histogram-based testing12.4.2 Spectral analysis method12.4.3 Walsh transform-based transfer function estimation12.4.4 Testing using sine-fit algorithms12.5 Delta-sigma modulator-based oscillator12.6 Digital signal processor interfacing with data converters12.6.1 Parallel interfacing12.6.2 Serial interfacing12.7 Built-in self-test structures for data converters12.8 Circuit design assessmentBibliography
13.1 Generation of clock signals with nonoverlapping phases13.2 Phase-locked loop13.2.1 PLL linear model13.2.2 Charge-pump PLL13.3 Charge-pump PLL building blocks13.3.1 Phase and frequency detector13.3.2 Phase detector13.3.2.1 Linear phase detector13.3.2.2 Binary phase detector13.3.2.3 Half-rate phase detector13.3.3 Charge-pump circuit13.3.4 Loop filter13.3.5 Voltage-controlled oscillator13.4 Applications13.4.1 Frequency synthesizer13.4.2 Clock and data recovery13.5 Delay-locked loop13.6 PLL with a built-in self-test structure13.7 PLL specifications13.8 Summary13.9 Circuit design assessmentBibliography
A.1 Boolean algebraA.1.1 Basic operationsA.1.2 Exclusive-OR and equivalence operationsA.2 Combinational logic circuitsA.2.1 Basic gatesA.2.2 CMOS implementationA.3 Sequential logic circuitsA.3.1 Asynchronous SR latchA.3.2 Asynchronous S R latchA.3.3 D latchA.3.4 D flip-flopsA.3.5 CMOS implementationA.4 Bibliography
B.1 MOS transistorB.2 AmplifierB.3 Comparator and latchB.4 Bibliography
C.1 SFG reduction rulesC.2 Mason’s gain formulaC.3 Bibliography

Content preview from CMOS Analog Integrated Circuits

Signal-Flow Graph

CONTENTS

C.1 SFG reduction rules

C.2 Mason’s gain formula

C.3 Bibliography

Signal-flow graphs (SFGs) [1] are suitable for the representation of continuoustime and discrete-time systems in the s-domain and z-domain, respectively. They can be considered a network diagram in which nodes are connected by unidirectional branches. Each node represents a system variable, and a scaling factor is indicated along each branch. The analysis and design of small and medium-size systems is often facilitated by the use of signal-flow graph techniques.

FIGURE C.1(a) Block diagram and (b) signal-flow graph representations of a system. ...

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ISBN: 9781439855003