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Computer System Designs: System-on-Chip by Wayne Luk, Michael J. Flynn

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INDEX

access time

accessing patterns

adaptive branch prediction

advanced encryption standard

advanced high-performance bus

AES

AHB

AMBA

analytic bus models

application, specific

instruction processors

integrated circuit

application studies

application throughput requirements

arbitration

architecture

architecture description

area

area model

ARM pipeline

array processors

ASICs

ASIP

ASOC

aspect ratio

associative mapped

asynchronous crossbar interconnect

asynchronous system

audio

autonomous optimization control

baseline dynamic network

baseline SOC area model

battery capacity

battery power

bimodal

block size

blocking

branch

elimination

history

management techniques

prediction

table buffer

target buffer

target capture

branch prediction

dynamic

static

branch speedup

branches

breaks

BTB

buffer

design

mean request

buffers

bus

bridge

transaction

varieties

wrappers

bus based approach

bus versus NOC

bypassing

cache

directory

hits

index

misses

offset

tag

cache data

cache memory

CAS

CGRA

chaining

Chebyshev’s inequality

chip floor planning

chip implanted credit card

CLBs

clock overhead

clock skew

coarse grained reconfigurable architecture

code density

column address strobe

combined prediction method

communication bandwidth

communication latency

communications laser

comparing networks

completion signal

complex programmable logic device

concurrent processors

condition code

configurability

configurable logic block

contention time

control flow scheduling

copy-back

CoreConnect bus

cost-performance ratio

CPLD

custom instructions

customisation

customizing instruction processors

cycle

cycle time

D-caches ...

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