Digital Systems: Principles and Design by Pearson

VHDL—Test Benches 17.11

Solution

Figure 17.2 shows the computer screen simulation of inputs A, B and C. ABC test

vectors are (“011”, “ 111”, and “000”) and output Y. Simulator shows that Y is ‘0’

for odd number of 1s in input vector of elements A, B and, C = 1, 1, and 1. The entity

stands tested and verified for three input vectors.

FIGURE 17.2 Computer screen simulation from a simulator for a XNOR circuit.

↓

120 ns

Name

0102030405060708090 100 110120

Initial

Value

Simulator

A

B

C

Y

0

0

1

1

Point to Remember

Behaviour visualization and counting number of errors can be on comparisons

of the responses expected from the available data in files or tables or lists ...