Digital Systems: Principles and Design by Pearson

18.14 Digital Systems: Principles and Design

How will you model RTL design entity and its behaviour for a JK-FF ? State Q and

complementary state Q1 is according to the inputs states at J and K at the instance

of −ve clock edge? Q1 is complementary logic state of Q.

Solution

Library IEEE ; -- VHDL using IEEE standard libraries

use IEEE.Std_Logic_1164.all ; -- import Std_Logic from the IEEE Library

use work.all;

entity JK_FF is

port (J, K, SeqClk, Reset0: in Std_Logic;

Q, Q1: out Std_Logic);

end JK_FF;

architecture RTLBehaviourJK_FF of JK_FF is

Signal Present_State: Std_Logic;

Signal JK_State: Std_Logic_Vector (1 downto 0);

begin

JK_State <= J & K ; -- concatenate ...