Electronic Packaging Science and Technology

2Cu‐to‐Cu and Other Bonding Technologies in Electronic Packaging

2.1 Introduction

Manufacturing of semiconductor devices can be divided into three portions: the front‐end‐of‐line (FEOL), the back‐end‐of‐line (BEOL), and the packaging. The FEOL deals with manufacturing of transistors, capacitors, and resistors. The BEOL refers to the fabrication processes after the deposition of the first metal layer, and there are more than 10 metal layers deposited by the dual‐damascene technique for Cu interconnects in high‐end devices. For the present 7 nm node, the first metal layer is Cu. The purpose for the BEOL is to connect the individual transistors, capacitors, and resistors. The final stage in semiconductor device packaging is to connect a chip or multiple chips to metal lead‐frames by wire bonding, to polyimide tapes by tape automatic bonding, to organic/ceramic substrates by solder joints, or to Si interposor or another chip by Cu‐to‐Cu bonds in the state‐of‐the‐art 3D integration of circuits (IC). Figure 2.1 shows the schematic drawing for the first‐level packaging on lead‐frame. The lead‐frames or the substrates with the chips are jointed to a print circuit board (PCB), which is called second‐level packaging. And then the PCB with chips are jointed to a mother board (third level packaging) if necessary in order to complete the packaging process. The packaging in movable hand‐held consumer products is about the same. The purposes for packaging are to provide signal passage, power ...