
Test Generation from Finite-State Models
q
3
q
1
q
2
a/1
b/1
b/1
a/0
b/1
a/0
q
3
q
1
q
2
a/1
b/1
a/0
b/1
a/0
b/1
(a) (b)
Fig. 3.23 State diagram of an FSM for which a test sequence derived using the UIO
approach does not reveal the error. (a) Specification FSM. (b) State diagram
of a faulty IUT.
Given below are tests for touring each of the nine core edges,
including three edges that bring each state to state q
1
upon reset.
Note that we have added the Re/null transition at the start of each
test sequence to indicate explicitly that the machine starts in state q
1
prior to the test being applied.
Test count Edge (e) TE(e)
Edges (e) from each state to state q
1
, label(e) = Re/
null ...