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FPGAs: World Class Designs

Name: FPGAs: World Class Designs
Author: Clive Maxfield
ISBN: 9780080950808

by Clive Maxfield

February 2009

Intermediate to advanced

488 pages

13h 51m

English

Newnes

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Brief Table of Contents
Table of Contents
Copyright
Preface
About the Editor
About the Contributors
Chapter 1. Alternative FPGA Architectures
1.1. A Word of Warning1.2. A Little Background Information1.3. Antifuse versus SRAM versus…1.4. Fine-, Medium-, and Coarse-Grained Architectures1.5. MUX- versus LUT-Based Logic Blocks1.6. CLBs versus LABs versus Slices1.7. Fast Carry Chains1.8. Embedded RAMs1.9. Embedded Multipliers, Adders, MACs, Etc1.10. Embedded Processor Cores (Hard and Soft)1.11. Clock Trees and Clock Managers1.12. General-Purpose I/O1.13. Gigabit Transceivers1.14. Hard IP, Soft IP, and Firm IP1.15. System Gates versus Real Gates1.16. FPGA Years
Chapter 2. Design Techniques, Rules, and Guidelines
2.1. Hardware Description Languages2.2. Top-Down Design2.3. Synchronous Design2.4. Floating Nodes2.5. Bus Contention2.6. One-Hot State Encoding2.7. Design For Test (DFT)2.8. Testing Redundant Logic2.9. Initializing State Machines2.10. Observable Nodes2.11. Scan Techniques2.12. Built-In Self-Test (BIST)2.13. Signature Analysis2.14. Summary
Chapter 3. A VHDL Primer
3.1. Introduction3.2. Entity: Model Interface3.3. Architecture: Model Behavior3.4. Process: Basic Functional Unit in VHDL3.5. Basic Variable Types and Operators3.6. Decisions and Loops3.7. Hierarchical Design3.8. Debugging Models3.9. Basic Data Types3.10. Summary
Chapter 4. Modeling Memories
4.1. Memory Arrays4.2. Modeling Memory Functionality4.3. VITAL_Memory Path Delays4.4. VITAL_Memory Timing Constraints4.5. Preloading Memories4.6. Modeling Other Memory Types4.7. Summary

Chapter 5. Introduction to Synchronous State Machine Design and Analysis
5.1. Introduction5.2. Models for Sequential Machines5.3. The Fully Documented State Diagram5.4. The Basic Memory Cells5.5. Introduction to Flip-Flops5.6. Procedure for FSM (Flip-Flop) Design and the Mapping Algorithm5.7. The D Flip-Flops: GeneralThe RET D Flip-FlopThe Master-Slave D Flip-Flop5.8. Flip-Flop Conversion: The T, JK Flip-Flops and Miscellaneous Flip-FlopsThe JK Flip-Flops and Their Design from D Flip-Flops5.9. Latches and Flip-Flops with Serious Timing Problems: A Warning5.10. Asynchronous Preset and Clear Overrides5.11. Setup and Hold Time Requirements of Flip-Flops5.12. Design of Simple Synchronous State Machines with Edge-Triggered Flip-Flops: Map Conversion5.13. Analysis of Simple State Machines5.14. VHDL Description of Simple State MachinesReferences
Chapter 6. Embedded Processors
6.1. Introduction6.2. A Simple Embedded Processor6.3. Soft Core Processors on an FPGA6.4. Summary
Chapter 7. Digital Signal Processing
7.1. Overview7.2. Basic DSP System7.3. Essential DSP Terms7.4. DSP Architectures7.5. Parallel Execution in DSP Components7.6. Parallel Execution in FPGA7.7. When to Use FPGAs for DSP7.8. FPGA DSP Design Considerations7.9. FIR Filter Concept Example7.10. Summary
Chapter 8. Basics of Embedded Audio Processing
8.1. Introduction8.2. Audio Sources and Sinks8.3. Interconnections8.4. Dynamic Range and Precision8.5. Audio Processing MethodsReferences
Chapter 9. Basics of Embedded Video and Image Processing
9.1. Introduction9.2. Broadcast TV—NTSC and PAL9.3. Color Spaces9.4. Digital Video9.5. A Systems View of Video9.6. Embedded Video Processing Considerations9.7. Compression/DecompressionReferences
Chapter 10. Programming Streaming FPGA Applications Using Block Diagrams in Simulink
10.1. Designing High-Performance Datapaths using Stream-Based Operators10.2. An Image-Processing Design Driver10.3. Specifying Control in Simulink10.4. Component Reuse: Libraries of Simple and Complex Subsystems10.5. Summary
BibliographyReferences
Chapter 11. Ladder and Functional Block Programming
11.1. Ladder Diagrams11.2. Logic Functions11.3. Latching11.4. Multiple Outputs11.5. Entering Programs11.6. Function Blocks11.7. Program Examples
Chapter 12. Timers
12.1. Types of Timers12.2. Programming Timers12.3. Off-Delay Timers12.4. Pulse Timers12.5. Programming Examples
Index
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Content preview from FPGAs: World Class Designs

Copyright

Preface

About the Editor

About the Contributors

Chapter 1. Alternative FPGA Architectures

1.1. A Word of Warning

1.2. A Little Background Information

1.3. Antifuse versus SRAM versus…

1.3.1. SRAM-Based Devices

1.3.2. Security Issues and Solutions with SRAM-Based Devices

1.3.3. Antifuse-Based Devices

1.3.4. EPROM-Based Devices

1.3.5. E2PROM/Flash-Based Devices

1.3.6. Hybrid Flash-SRAM Devices

1.3.7. Summary

1.4. Fine-, Medium-, and Coarse-Grained Architectures

1.5. MUX- versus LUT-Based Logic Blocks

1.5.1. MUX-Based

1.5.2. LUT-Based

1.5.3. MUX-Based versus LUT-Based?

1.5.4. 3-, 4-, 5-, or 6-Input LUTs?

1.5.5. LUT versus Distributed RAM versus SR

1.6. CLBs versus LABs versus Slices

1.6.1. A Xilinx Logic Cell ...

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Publisher Resources

ISBN: 9781856176217

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FPGAs: World Class Designs

by Clive Maxfield

Table of Contents

Become an O’Reilly member and get unlimited access to this title plus top books and audiobooks from O’Reilly and nearly 200 top publishers, thousands of courses curated by job role, 150+ live events each month,
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