
and the ADIF interrupt flag is set. Since the result is only 10 bits, the posi-
tioning in the 16-bit result register pair can be selected, so that the high 8 bits
are in ADRESH (left justified), or the low 8 bits are in ADRESL (right justi-
fied) (Figure 7.2 (c)). Obviously, to retain 10-bit resolution, both parts must be
processed, so right justification will probably be more convenient in this case.
If only 8 bits resolution is required, the process can be simplified. If the result
is right justified, the low 8 bits in ADRESL will record the low bits of the
conversion, meaning that only voltages up to 25% of the full range will be
processed, but ...