Learning FPGAs

Chapter 11. Advanced Timing and Clock Domains

In this chapter, we will look at what happens when you break timing and some ways to fix the problem. We will also talk about having multiple clocks in your design and how to reliably get data between clock domains. This can be tricky because usually you can’t ensure the that clocks are aligned or they aren’t perfect multiples of each other. If you try to feed a signal synchronized to one clock into a DFF running off another clock, you will violate timing constraints periodically.

After finishing this chapter, you should know how to identify timing problems and know some techniques to fix them. This includes timing issues that the tools try to avoid when laying out and routing your design and issues that arise due to your design.

Breaking Timing and Fixing It with Pipelining

In this  section, we are going to create a design that intentionally breaks timing by giving the tools an impossible task of performing a bunch of multiplications in a single clock cycle. We will identify the issue by looking at the timing report generated by the tools and then fix the design by splitting the operation into multiple clock cycles.

If you are using the 50 MHz clock on the Mojo without changing the frequency, you won’t likely run into timing issues for your designs. However, it is still quite possible to break timing, and we’ll take a look at a technique known as pipelining that can be used to help timing.

To demonstrate this, we need a design that ...