Sequential addressing
Yes, this is not a typo, there is sequential addressing when it comes to addressing data as well, although it does require certain setup.
Remember the RSI/RDI pair (or ESI/EDI for 32-bit systems), which we have mentioned in both Chapter 1, Intel Architecture, and Chapter 3, Intel Instruction Set Architecture (ISA). This pair is a good example of sequential data addressing, where the source and/or target addresses are incremented or decremented (depending on the value of the direction flag) automatically after each instruction that uses these registers (either one of them or both) has been executed.
The following example illustrates this mode by copying a text string from its location in the data section to a buffer allocated ...
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